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sn8p 27 40 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 1 versi on 1. 6 sn8p27 40 series users manual version 1. 6 sn8p2743 sn8p2742 sn8p2741 1 s s o o n n i i x x 8 8 - - b b i i t t m m i i c c r r o o - - c c o o n n t t r r o o l l l l e e r r sonix reserves the right to make change without further notice to any products herein to improve reliability, function or de sign . sonix does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. sonix products are not designed, intended, or a uthorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the f ailure of the sonix product could create a situation where persona l injury or death may occur. should buyer purchase or use sonix products for any such unintended or unauthorized application. buyer shall indemnify and hold sonix and its officers, employees, subsidiaries, affiliates and distributors harmless against all c laims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manufacture of the part.
sn8p 27 40 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 2 versi on 1. 6 amendent history version date description ver 0. 1 oct. 2009 first issue. ver 0. 2 mar . 20 10 1. fix typing errors of feature table. 2. fix typing errors of bit definition of system registers. 3. fix typing errors of i/o sh ared pin table. 4. add p0 application notices. 5. modify p0.1 to write only type. 6. modify tc0 pulse width table. 7. add tc0enb control notice in comparator 1 special function . 8. modify op - amp pin definition. 9. add development tools description. 10. modify electrical c haracteristic section. ver 0. 3 apr. 20 10 1. modify the pin assignments of sn8p2742p and sn8p2742s. 2. modify programming pin mapping table for sn8p2742p and sn8p2742s. 3. modify development tool for sn8p2742. ver 0. 4 jun. 20 10 1. modify ev - kit version from a to v1.0 . 2. modify ev2740 ev - kit schematic / outline. 3. modify development tool chapter. ver 1.0 may. 2011 1. version update. 2. modify development tool description 3. modify chapter 16.3 characteristic graphs ver 1. 1 may. 2011 1. modify chapter 10.4 comparat or mode register cmdb0 register bit3 cm1d3 >> cm0d3. 2. modify chapter 13.1 overview description : it is necessary to set p4 as input mode with pull - up resistor by program >> it is necessary to set p4 as input mode without pull - up resistor by program ver 1.2 sep. 2011 1. add sn8p2741 pin assignment and modify some chapters ver 1.3 dec. 2011 1. delete sn8p2741 pin assignment and the others. 2. add SN8P27411 pin assignment and the others. ver 1.4 may. 2012 1. modify SN8P27411 pin assignment. ver 1.5 oct. 2012 modify SN8P27411 pin assignment. ver 1.6 nov. 2012 modify electrical characteristic with op amp characteristic .
sn8p 27 40 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 3 versi on 1. 6 table of content amendent history ................................ ................................ ................................ ................................ 2 1 1 1 product overview ................................ ................................ ................................ ......................... 7 1.1 features ................................ ................................ ................................ ................................ ........ 7 1.2 system block diagram ................................ ................................ ................................ .......... 8 1.3 pin assignment ................................ ................................ ................................ ........................... 8 1.4 pin descriptions ................................ ................................ ................................ ......................... 9 1.5 pin circuit diagrams ................................ ................................ ................................ ............. 10 2 2 2 central processor un it (cpu) ................................ ................................ .............................. 13 2.1 program memory (rom) ................................ ................................ ................................ ....... 13 2.1.1 reset vector (0000h) ................................ ................................ ................................ ...... 14 2.1.2 interrupt vector (0008h) ................................ ................................ ............................. 15 2.1.3 look - up table description ................................ ................................ ........................ 17 2.1.4 jump table description ................................ ................................ ............................... 19 2.1.5 checksum calculation ................................ ................................ ............................... 21 2.2 data memory (ram) ................................ ................................ ................................ ................ 22 2.2.1 system register ................................ ................................ ................................ .............. 22 2.2.1.1 system register table ................................ ................................ ............................ 22 2.2.1.2 system register description ................................ ................................ ............... 22 2.2.1.3 bit definition of system register ................................ ................................ ....... 23 2.2.2 accumulator ................................ ................................ ................................ ................... 25 2.2.3 progr am flag ................................ ................................ ................................ ................... 26 2.2.4 program counter ................................ ................................ ................................ ........... 27 2.2.5 h, l registers ................................ ................................ ................................ ..................... 30 2.2. 6 y, z registers ................................ ................................ ................................ ..................... 31 2.2.7 r register ................................ ................................ ................................ ........................... 31 2.3 addressing mode ................................ ................................ ................................ .................... 32 2 .3.1 immediate addressing mode ................................ ................................ .................... 32 2.3.2 directly addressing mode ................................ ................................ ....................... 32 2.3.3 indirectly addressing mode ................................ ................................ ................... 32 2.4 stack operation ................................ ................................ ................................ ...................... 33 2.4.1 overview ................................ ................................ ................................ ............................. 33 2.4.2 stack registers ................................ ................................ ................................ ............... 34 2.4.3 stack operation example ................................ ................................ .......................... 35 2.5 code option table ................................ ................................ ................................ .................. 36 2.5.1 fcpu code option ................................ ................................ ................................ ...................... 36 2.5.2 reset_pin code option ................................ ................................ ................................ .............. 36 2.5.3 security code option ................................ ................................ ................................ ................. 36 3 3 3 res et ................................ ................................ ................................ ................................ ..................... 37 3.1 overview ................................ ................................ ................................ ................................ ..... 37 3.2 power on reset ................................ ................................ ................................ ......................... 38 3.3 watchdog reset ................................ ................................ ................................ ...................... 38 3.4 brown out reset ................................ ................................ ................................ ..................... 38 3.5 the system operating voltage ................................ ................................ ....................... 39 3.6 low voltage detector (lvd) ................................ ................................ ............................ 39 3.7 brown out reset improvement ................................ ................................ ....................... 41 3.8 external reset ................................ ................................ ................................ ........................ 42 3.9 external reset circuit ................................ ................................ ................................ ....... 42 3.9.1 simply rc reset circuit ................................ ................................ ................................ .......... 42
sn8p 27 40 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 4 versi on 1. 6 3.9.2 diode & rc reset circuit ................................ ................................ ................................ ........ 43 3.9.3 zener diode reset circuit ................................ ................................ ................................ ........ 43 3.9.4 voltage bias reset circuit ................................ ................................ ................................ ....... 44 3.9.5 external reset ic ................................ ................................ ................................ ...................... 44 4 4 4 system clock ................................ ................................ ................................ ................................ .. 45 4.1 overview ................................ ................................ ................................ ................................ ..... 45 4.2 f cpu (instruction cycle) ................................ ................................ ................................ ...... 45 4.3 system high - speed clock ................................ ................................ ................................ .... 45 4.3.1 high_clk code option ................................ ................................ ................................ ... 46 4.3.2 internal high - speed oscillator rc type (ihrc) ................................ ............. 46 4.3.3 external high - speed oscillator ................................ ................................ ........... 46 4.3.4 e xternal oscillator application circuit ................................ ....................... 46 4.4 system low - speed clock ................................ ................................ ................................ ..... 47 4.5 oscm register ................................ ................................ ................................ ........................... 48 4.6 system clock measurement ................................ ................................ ............................. 48 4.7 system clock timing ................................ ................................ ................................ ............. 49 5 5 5 system operation mod e ................................ ................................ ................................ ........... 52 5.1 overview ................................ ................................ ................................ ................................ ..... 52 5.2 normal mode ................................ ................................ ................................ ............................ 53 5.3 slow mode ................................ ................................ ................................ ................................ .. 53 5.4 power down mode ................................ ................................ ................................ .................. 53 5.5 green mode ................................ ................................ ................................ ................................ 54 5.6 operating mode control macro ................................ ................................ .................... 55 5.7 wakeup ................................ ................................ ................................ ................................ ......... 56 5.7.1 overview ................................ ................................ ................................ ............................. 56 5.7.2 wakeup time ................................ ................................ ................................ ...................... 56 5.7.3 p1w wakeup control register ................................ ................................ ................ 57 6 6 6 interrupt ................................ ................................ ................................ ................................ ........... 58 6.1 overview ................................ ................................ ................................ ................................ ..... 58 6.2 inten interrupt enable register ................................ ................................ ................... 59 6.3 intrq interrupt request register ................................ ................................ ................ 60 6.4 gie global interrupt operation ................................ ................................ .................... 61 6.5 push, pop routine ................................ ................................ ................................ ..................... 62 6.6 external interrupt operation (int0) ................................ ................................ ........... 63 6.7 t0 interrupt operation ................................ ................................ ................................ ........ 64 6.8 tc0 interrupt operation ................................ ................................ ................................ ..... 65 6.9 adc interrupt operation ................................ ................................ ................................ ... 66 6.10 comparator interrupt operation (cmp0~cmp2) ................................ ...................... 67 6.11 multi - interrupt operation ................................ ................................ ............................... 68 7 7 7 i/o port ................................ ................................ ................................ ................................ ................ 69 7.1 overview ................................ ................................ ................................ ................................ ..... 69 7.2 i/o port mode ................................ ................................ ................................ ............................. 70 7.3 i/o pull up register ................................ ................................ ................................ ................ 71 7.4 i/o port data register ................................ ................................ ................................ .......... 72 7.5 port 4 adc share pin ................................ ................................ ................................ ............... 73 8 8 8 timers ................................ ................................ ................................ ................................ .................. 76 8.1 watchdog timer ................................ ................................ ................................ ...................... 76 8.2 t0 8 - bit basic timer ................................ ................................ ................................ ................. 78 8.2.1 overview ................................ ................................ ................................ ............................. 78 8.2.2 t0 timer operation ................................ ................................ ................................ ......... 78 8.2.3 t0m mode register ................................ ................................ ................................ ......... 79 8.2.4 t0c counting register ................................ ................................ ................................ . 79
sn8p 27 40 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 5 versi on 1. 6 8.2.5 t0 timer operation explame ................................ ................................ ..................... 80 8.3 tc0 8 - bit timer/co unter ................................ ................................ ................................ ....... 81 8.3.1 overview ................................ ................................ ................................ ............................. 81 8.3.2 tc0 timer operation ................................ ................................ ................................ ...... 82 8.3.3 pu lse width modulation (pwm) ................................ ................................ .............. 83 8.3.4 tc0 pulse generator function ................................ ................................ ................................ . 84 8.3.5 tc0m mode register ................................ ................................ ................................ ....... 86 8.3.6 tc0c counting register ................................ ................................ .............................. 86 8.3.7 tc0r auto - reload register ................................ ................................ ....................... 87 8.3.8 tc0d pwm duty register ................................ ................................ ............................. 87 8.3.9 tc0 timer operation explame ................................ ................................ .................. 88 9 9 9 analog comparaotr 0 ................................ ................................ ................................ ............... 90 9.1 overview ................................ ................................ ................................ ................................ ..... 90 9.2 normal comparator mode ................................ ................................ ................................ 91 9.3 comparator 0 special fucniton ................................ ................................ ...................... 93 9.4 comparator mode register ................................ ................................ .............................. 94 9.5 comparator application notice ................................ ................................ .................... 94 9.6 comparator 0 operation explame ................................ ................................ ................ 95 1 1 1 0 0 0 analog comparaotr 1 ................................ ................................ ................................ ........... 96 10.1 overview ................................ ................................ ................................ ................................ ..... 96 10.2 normal comparator mode ................................ ................................ ................................ 97 10.3 comparator 1 special fucniton ................................ ................................ ...................... 99 10.4 comparator mode register ................................ ................................ ............................ 100 10.5 comparator application notice ................................ ................................ .................. 101 10.6 comparator 1 operation explame ................................ ................................ .............. 101 1 1 1 1 1 1 analog comparaotr 2 ................................ ................................ ................................ ......... 102 11.1 overview ................................ ................................ ................................ ................................ ... 102 11.2 normal comparator mode ................................ ................................ .............................. 103 11.3 comparator 2 s pecial fucniton ................................ ................................ .................... 105 11.4 comparator mode register ................................ ................................ ............................ 106 11.5 comparator application notice ................................ ................................ .................. 107 11.6 comparator 2 operation explame ................................ ................................ .............. 107 1 1 1 2 2 2 2k/4k buzzer generat or ................................ ................................ ................................ ..... 108 12.1 overview ................................ ................................ ................................ ................................ ... 108 12.2 bzm register ................................ ................................ ................................ ............................ 108 1 1 1 3 3 3 8 channel analog to digital converter (a dc) ................................ ................... 109 13 .1 overview ................................ ................................ ................................ ................................ ... 109 13.2 adc mode register ................................ ................................ ................................ ............... 110 13.3 adc data buffer registers ................................ ................................ .............................. 111 13.4 adc operation description and notic ................................ ................................ ....... 112 13.4.1 adc signal format ................................ ................................ ................................ ...... 112 13.4.2 adc converting time ................................ ................................ ................................ .. 1 12 13.4.3 adc pin configuration ................................ ................................ .............................. 113 13.5 adc operation examlpe ................................ ................................ ................................ ..... 114 13.6 adc application circuit ................................ ................................ ................................ ......... 116 1 1 1 4 4 4 rail to rail op ampl ifer ................................ ................................ ................................ .... 117 14.1 overview ................................ ................................ ................................ ................................ ... 117 14.2 op amp register ................................ ................................ ................................ ...................... 117 1 1 1 5 5 5 instruction table ................................ ................................ ................................ ................. 118 1 1 1 6 6 6 electrical character istic ................................ ................................ ............................ 119 16.1 absolute maximum rating ................................ ................................ .............................. 119 16.2 electrical characteristic ................................ ................................ ............................. 119
sn8p 27 40 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 6 versi on 1. 6 16.3 characteristic graphs ................................ ................................ ................................ ..... 121 1 1 1 7 7 7 development tool ................................ ................................ ................................ ................ 122 17.1 sn8p2740 ev - kit ................................ ................................ ................................ .......................... 122 17.2 ice and ev - kit application notic ................................ ................................ .................... 124 1 1 1 8 8 8 otp programming pin ................................ ................................ ................................ ........... 126 18.1 writer transition board socket pin assignment ................................ ............... 126 18.2 programming pin mapping: ................................ ................................ ............................... 127 1 1 1 9 9 9 marking definition ................................ ................................ ................................ ............... 128 19.1 introduction ................................ ................................ ................................ .......................... 128 19.2 marking indetification system ................................ ................................ .................... 128 19.3 marking example ................................ ................................ ................................ ................. 128 1 9.4 datecode system ................................ ................................ ................................ .................. 129 2 2 2 0 0 0 package information ................................ ................................ ................................ ......... 130 20.1 sk - dip 24 pin ................................ ................................ ................................ ............................... 130 20.2 sop 24 pin ................................ ................................ ................................ ................................ ..... 131 20.3 p - dip 20 pin ................................ ................................ ................................ ................................ .. 132 20.4 sop 20 pin ................................ ................................ ................................ ................................ ..... 133 20.5 p - dip 16 pin ................................ ................................ ................................ ................................ .. 134 20.6 sop 16 pin ................................ ................................ ................................ ................................ ..... 135
sn8p 27 40 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 7 versi on 1. 6 1 1 1 product overview 1.1 features ? features selection table chip rom ram stack timer pwm pulse generator buzzer ext. int i/o adc op - amp comp - arator package t0 tc0 sn8p2743 4k*16 128*8 8 v v 1 1 1 1 22 8 - ch 1 3 skdip24 sop24 sn8p2742 4k*16 128*8 8 v v 1 1 1 - 18 6 - ch 1 3 pdip20 sop20 sn8p2741 1 4k*16 128*8 8 v v 1 1 1 - 1 4 6 - ch 1 3 pdip 16 sop 16 ? memory configuration ? one 8 - bit basic timer. (t0). rom size: 4k * 16 bits . ? one 8 - bit timer with pwm and pulse generator ram size: 128 * 8 bits. (tc0). ? one 2k/4k programmable buzzer output. ? 8 levels stack buffer. ? 8 - channel 12 - bit sar adc. ? 7 interrupt sources ? 1 - set rail - to - rail op - amp. 6 internal int errupts: t0, tc0, adc, cm0, cm1, cm2 ? 3 - set comparators. 1 external interrupt: int0 ? on chip watchdog timer and clock source is internal low clock rc type (16khz @3v, 32khz ? i/o pin configuration @5v). bi - directional: p0, p1, p4. wakeu p: p0, p1 level change. ? 4 system clocks pull - up resisters: p0, p1, p4. external high clock: rc type up to 10 mhz op - amp/comparator pins: p1, p4. external high clock: crystal type up to 16 mhz adc input pin: p4.0~p4.7. internal high clock: rc typ e 16mhz internal low clock: rc type 16khz(3v), 32khz(5v) ? fcpu (instruction cycle) fcpu = fosc/4, fosc/8, fosc/16. ? 4 operating modes normal mode: both high and low clock active ? 3 - level lvd slow mode: low clock only. 2.0v/2.4v/3.6v s leep mode: both high and low clock stop green mode: periodical wakeup by timer ? powerful instructions instruction?s length is one word. ? package (chip form support) most of instructions are one cycle only. sk dip 24 pin all rom area jmp/call instruction. pdip 20 pin all rom area lookup table function (movc). sop 24 pin sop 20 pin pdip 16 pin sop 16 pin
sn8p 27 40 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 8 versi on 1. 6 1.2 system block diagram 1.3 pin assignment sn8p2743 k ( skdip 24 pin) sn8p2743 s ( sop 24 pin) vss 1 u 24 vdd xin/p0.6 2 23 p4.7/ain7 xout/p0.5/bz 3 22 p4.6/ain6 rst/vpp/p0.4 4 21 p4.5/ain5 p0.0/int0 5 20 p4.4/ain4 p0.1/pwm0 6 19 p4.3/ain3/cm0o p0.2/cm0p 7 18 p4.2/ain 2/cm1o p0.3/cm0n 8 17 p4.1/ain1/cm2o p1.6/cm1p 9 16 p4.0/ain0/avrefh p1.5/cm1n 10 15 p1.0/opn p1.4/cm2p 11 14 p1.1/opp p1.3/cm2n 12 13 p1.2/opo sn8p2742 p ( dip 20 pin) sn8p2742 s ( sop 20 pin) vss 1 u 20 vdd xin/p0.6 2 19 p4. 5 /ain 5 xout/p0.5/bz 3 18 p4.4/ain4 rst/vpp/p0.4 / p0.1/pwm0 4 17 p4.3/ain3/cm0o p0.2/cm0p 5 16 p4.2/ain2/cm1o p0.3/cm0n 6 15 p4.1/ain1/cm2o p1.6/cm1p 7 14 p4.0/ain0/avrefh p1.5/cm1n 8 13 p1.0/opn p1.4/cm2p 9 12 p1.1/opp p1.3/cm2n 10 11 p1.2/opo i n t e r r u p t c o n t r o l e x t e r n a l h i g h o s c . a c c i n t e r n a l l o w r c t i m i n g g e n e r a t o r r a m s y s t e m r e g i s t e r s 3 - l e v e l l v d ( l o w v o l t a g e d e t e c t o r ) w a t c h d o g t i m e r t i m e r & c o u n t e r p 0 p 1 p w m & p u l s e o u t p u t a l u p c f l a g s i r o t p r o m p 4 i n t e r n a l h i g h r c 1 6 m h z c o m p a r a t o r 0 c o m p a r a t o r 1 1 2 - b i t a d c a i n 0 ~ a i n 7 c o m p a r a t o r 2 o p a c m 0 n , c m 0 p , c m 0 o o p n , o p p , o p o p w m 0 b u z z e r b z c m 2 n , c m 2 p . c m 2 o c m 1 n , c m 1 p , c m 1 o
sn8p 27 40 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 9 versi on 1. 6 sn8p274 1 1 p ( dip 16 pin) v dd 1 u 16 p4. 7 /ain 7 xout/p0.5/bz 2 1 5 p4. 6 /ain 6 rst/vpp/p0.4/ p0.1/pwm0 3 1 4 p4.4/ain4 p0.2/cm0p 4 1 3 vss p0.3/cm0n 5 1 2 p4.2/ain2/cm1o p1.5/cm1n 6 1 1 p4.1/ain1/cm2o p1.3/cm2n 7 1 0 p4.0/ain0/avrefh p4.3/opo 8 9 p1.0/opn ? opp (op a s positive pin) pin connects to ground. sn8p274 1 1 s ( sop 16 pin) v dd 1 u 16 vss xout/p0.5/bz 2 1 5 p4. 7 /ain 7 rst/vpp/p0.4/ p0.1/pwm0 3 1 4 p4. 6 /ain 6 p0.2/cm0p 4 1 3 p4.4/ain4 p0.3/cm0n 5 1 2 p4.2/ain2/cm1o p1.5/cm1n 6 1 1 p4.1/ain1/cm2o p1.3/cm2n 7 1 0 p4.0/ain0/avrefh p4.3/opo 8 9 p1.0/opn ? opp (opa s positive pin ) pin connects to ground. 1.4 pin descriptions pin name type description vdd, vss p power supply input pins for digital and analog circuit. p0.4/rst/vpp i, p rst: system external reset in put pin. schmitt trigger structure, active low, normal stay to high. vpp: otp 12.3v power input pin in programming mode. p0.4: input only pin with schmitt trigger structure and no pull - up resistor. level change wake - up. xin/p0.6 i/o xin: oscil lator input pin while external oscillator enable (crystal and rc). p0.6: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. level change wake - up. xout/p0.5/bz i/o xout: oscillator output pin while external crystal en able. p0.5: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. level change wake - up. bz: 2k/4k programmable buzzer output pin. p0.0/int0 i/o p0.0: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. int0: external interrupt 0 input pin. p0.1/pwm0 i/o p0.1: output pin with open - drain structure. pwm0: pwm output pin and pulse output pin. p0.2/cm0p i/o p0.2: bi - direction pin. schmitt trigger structure as input mode. buil t - in pull - up resisters. level change wake - up. cm0p: the positive input pin of comparator. p0.2/cm0n i/o p0.3: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. level change wake - up. cm0n: the negative input pin of comparator. p1.0/opn i/o p1.0: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. level change wake - up. opn: the negative input pin of op amp. p1.1/opp i/o p1.1: bi - direction pin. schmitt trigger structure as i nput mode. built - in pull - up resisters. level change wake - up. opp: the positive input pin of op amp. p1.2/opo i/o p1.2: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. level change wake - up. opo: the output pin of op amp.
sn8p 27 40 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 10 versi on 1. 6 p1.3/cm2n i/o p1.3: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. level change wake - up. cm2n: the negative input pin of comparator. p1.4/cm2p i/o p1.4: bi - direction pin. schmitt trigger structure a s input mode. built - in pull - up resisters. level change wake - up. cm2p: the positive input pin of comparator. p1.5/cm1n i/o p1.5: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. level change wake - up. cm1n: the n egative input pin of comparator. p1.6/cm1p i/o p1.6: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. level change wake - up. cm1p: the positive input pin of comparator. p4.0/ain0/avrefh i/o p4.0: bi - direction pi n. schmitt trigger structure as input mode. built - in pull - up resisters. ain0: adc analog input pin. avrefh: adc reference high voltage input pin. p4.1/ain1/cm2o i/o p4.1: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. ain1: adc analog input pin. cm2o: the output pin of comparator. p4.2/ain2/cm1o i/o p4.2: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. ain2: adc analog input pin. cm1o: the output pin of comparator. p4.3/ain3/cm0o i/o p4.3: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. ain3: adc analog input pin. cm0o: the output pin of comparator. p4.4/ain4 i/o p4.4: bi - direction pin. schmitt trigger str ucture as input mode. built - in pull - up resisters. ain4: adc analog input pin. p4.5/ain5 i/o p4.5: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. ain5: adc analog input pin. p4.6/ain6 i/o p4.6: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. ain6: adc analog input pin. p4.7/ain7 i/o p4.7: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. ain7: adc analog input pin. refer to ad c section. 1.5 pin circuit diagrams ? reset shared pin structure: ? oscillator shared pin structure: ? gpio structure: p i n e x t . r e s e t c o d e o p t i o n i / o i n p u t b u s r e s e t p u l l - u p r e s i s t o r o u t p u t l a t c h p i n p n u r p n m i / o i n p u t b u s i / o o u t p u t b u s p n m h i g h _ c l k c o d e o p t i o n o s c i l l a t o r d r i v e r
sn8p 27 40 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 11 versi on 1. 6 ? p0.1: open - drain shared pin, output only i/o: p u l l - u p r e s i s t o r o u t p u t l a t c h p i n p n u r p n m i / o i n p u t b u s i / o o u t p u t b u s p n m p i n o p e n - d r a i n c o n t r o l i / o b u s r v c c i n s i d e o u t s i d e
sn8p 27 40 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 12 versi on 1. 6 ? adc shared pin with reference high voltage structure : ? adc shared pin structure : ? op - amp shared pins structure : ? comparator shared pins structure : comparator negative pin: comparator positive pin: comparator output pin: a v r e f h a v r e f h p i n g c h s p 4 c o n a d c i n p u t p u l l - u p r e s i s t o r o u t p u t l a t c h p n u r p n m i / o i n p u t b u s i / o o u t p u t b u s p n m a d e n b p i n a d e n b , g c h s p 4 c o n a d c i n p u t p u l l - u p r e s i s t o r o u t p u t l a t c h p n u r p n m i / o i n p u t b u s i / o o u t p u t b u s p n m p i n o p n e n o p - a m p t e r m i n a l p u l l - u p r e s i s t o r o u t p u t l a t c h p n u r p n m i / o i n p u t b u s i / o o u t p u t b u s p n m p i n c m n e n c o m p a r a t o r n e g a t i v e i n p u t p u l l - u p r e s i s t o r o u t p u t l a t c h p n u r p n m i / o i n p u t b u s i / o o u t p u t b u s p n m p i n c m n e n c o m p a r a t o r p o s i t i v e i n p u t p u l l - u p r e s i s t o r o u t p u t l a t c h p n u r p n m i / o i n p u t b u s i / o o u t p u t b u s p n m c m n r e f p i n c m n e n c o m p a r a t o r o u t p u t p u l l - u p r e s i s t o r o u t p u t l a t c h p n u r p n m i / o i n p u t b u s i / o o u t p u t b u s p n m c m n o e n
sn8p 27 40 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 13 versi on 1. 6 2 2 2 central processor unit (cpu) 2.1 program memory (rom) ? 4k word s rom rom 0000h reset vector us er reset vector jump to user start address 0001h general purpose area . . 0007h 0008h interrupt vector user interrupt vector 0009h general purpose area user program . . 000fh 0010h 0011h . . . . . 0f f ch end of u ser program 0f f dh reserved 0f f eh 0f f fh the rom includes reset vector, interrupt vector, general purpose area and reserved area. the reset vector is program beginning address. the interrupt vector is the head of interrupt service routine when any interrupt occurring. the general purpose area is main program area including main loop, sub - routines and data table.
sn8p 27 40 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 14 versi on 1. 6 2.1.1 reset vector (0000h) a one - word vector address area is used to execute system reset. ? power on reset (nt0=1, npd=0). ? watchdog reset (nt0=0, npd=0). ? external reset (nt0=1, npd=1). after power on reset , external reset or watchdog timer overflow reset , then the chip will restart the program from address 0000h and all system registers will be set as default values. it is easy to know res et status from nt0, npd flags of pflag register. the following example shows the way to define the reset vector in the program memory. ? example : defining reset vector org 0 ; 0000h jmp start ; jump to user program address. org 10h start: ; 00 10 h, the head of user program. endp ; end of program
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 15 version 1. 6 2.1.2 interrupt vector (0008h) a 1 - word vector address area is used to execute interrupt request. if any interrupt service executes, the program counter (pc) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt. users have to define the interrupt vector . the following example shows the way to define the interrupt vector in the program memory. ? note: push , pop instructions save and load acc/pflag without ( nt0, npd). push/pop buffer is a unique buffer and only one level. ? example: defining interrupt vector. the interrupt service routine is following org 8. .code org 0 ; 0000h jmp start ; jump to user program address. org 8 ; interrupt vector. push ; save acc and pflag register to buffers. pop ; load acc and pflag register from buffers. reti ; end of interrupt service routine
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 16 version 1. 6 ? example: defining interrupt vector. the interrupt service routine is following user program. .code org 0 ; 0000h jmp start ; jump to user program address. org 8 ; interrupt vector. jmp my_ irq ; 0008h, jump to interrupt service routine address. org 10 h start: ; 0010h, the head of user program. my _ i r q : ;the head of interrupt service routine. push ; save acc and pflag register to buffers. pop ; load acc and pflag register from buffers. reti ; end of interrupt service routine. ? note: it is easy to understand the rules of sonix program from demo programs given above. these points are as following: 1. the address 0000h is a jmp instruction to make the program starts from the beginning . 2. the address 0008h is interrupt vector. 3. user s progra m is a loop routine for main purpose application.
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 17 version 1. 6 2.1.3 look - up table description in the rom?s data lookup function, y register is pointed to middle byte address ( bit 8~bit 15 ) and z register is pointed to low byte address ( bit 0~bit 7 ) of rom. after movc instruction executed, the low - byte data will be stored in acc and high - byte data stored in r register. ? example: to look up the rom data located table1. b0mov y, #table1$m ; to set lookup table1?s middle address able1?s low address. ; increment the index address for next address . incms z ; z+1 jmp @f ; z is n ot overflow . incms y ; z overflow (ffh ? 00), ? y= y+1 nop ; ; @@: movc ; to lookup data, r = 51h, acc = 05h. ? note : the y register will not increase automatically when z register cross es boundary from 0xff to 0x00. therefore, user mus t be take care such situation to avoid loo k - up table errors. if z register is overflow, y register must be added one. the following inc_yz macro shows a simple method to process y and z registers automatically. ? example: inc_yz macro . inc_yz macro incms z ; z+1 jmp @f ; not overflow incms y ; y+1 nop ; not overflow @@: endm
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 18 version 1. 6 ? example: modify above example by inc_yz macro . b0mov y, #table1$m ; to set lookup table1?s middle address lookup table1?s low address. inc_yz ; increment the index address for next address . ; @@: movc ; to lookup data, r = 51h, acc = 05h. be careful if carry happen. ? example: increase y and z register by b0add/add instruction . b0mov y, #table1$m ; to se t lookup table?s middle address. ; to set lookup table?s low address. b0mov a, buf ; z = z + buf. b0add z, a b0bts1 fc ; check the carry flag. jmp getdata ; fc = 0 incms y ; fc = 1. y+1. nop getdata: ; movc ; to lookup data. if buf = 0, data is 0x0035 ; if buf = 1, data is 0x5105 ; if buf = 2, data is 0x2012
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 19 version 1. 6 2.1.4 jump tabl e description the jump table operation is one of mu l ti - address jumping function . add low - byte program counter (pcl) and acc value to get one new pcl. if pcl is overflow after pcl+acc, pch adds one automatically. the new program counter (pc) points to a ser ies jump instructions as a listing table. i t is easy to make a mu l ti - jump program depends on the value of the accumulator (a) . ? note: pch only support pc up counting result and doesn t support pc down counting. when pcl is carry after pcl+acc, pch adds on e automatically. if pcl borrow after pcl C acc, pch keeps value and not change. ? example: jump table. org 0x0100 ; the jump table is from the head of the rom boundary b0add pcl, a ; pcl = pcl + acc, pch + 1 when pcl overflow occurs . jmp a0po int ; acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point sonix provides a macro for safe jump table function. this macro will check the rom boundary and move the jump table to the right position automatically. the side effect of this macro maybe wastes some rom size. ? example: if jump table crosses over rom boundary will cause errors. @jmp_a macro val if (($+1) !& 0xff00) !!= (($+(val)) !& 0xff00) jmp ($ | 0xff) org ($ | 0xff) endif b0 add pcl, a endm ? note: val is the number of the jump table listing number. ? example: @jmp_a application in sonix macro file called macro3.h . b0mov a, buf0 ;
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 20 version 1. 6 if the jump table position is across a rom boundary (0x00ff~0x0100), the @jmp_a macro will adjust the jump table routine begin from next ram boundary (0x0100). ? example: @jmp_a operation. ; before compiling program. rom address b0mov a, buf0 ; ; after compiling program. rom address b0mov a, buf0 ;
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 21 version 1. 6 2.1.5 checksum calculation the last rom address are reserved area. user should avoid these addresses (last address) when calculate the checksum value. ? example: the demo program shows how to calculated checksum from 00h to the end of users code . mov a,#end_user_code$l b0mov end_a ddr1, a ; s ave low end address to end_addr1 mov a,#end_user_code$m b0mov end_addr2, a ; s ave middle end address to end_addr2 clr y ; s et y to 00h clr z ; s et z to 00h @@: movc b0bset fc ; c lear c f lag add data1, a ; a dd a to data1 mo v a, r adc data2, a ; a dd r to data2 jmp end_check ; c heck if the yz address = the end of code aaa: incms z ; z=z+1 jmp @b ; if z != 00h calculate to next address jmp y_add_1 ; i f z = 00h increase y end_check: mov a, end_addr1 cmp rs a, z ; c heck if z = low end address jmp aaa ; i f not jump to checksum calculate mov a, end_addr2 cmprs a, y ; i f yes, check if y = middle end address jmp aaa ; i f not jump to checksum calculate jmp checksum_end ; i f yes checksum calculated is done. y_add_1: incms y ; i ncrease y nop jmp @b ; j ump to checksum calculate checksum_end: end_user_code: ; label of program end
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 22 version 1. 6 2.2 data memory (ram) ? 128 x 8 - bit ram address ram l ocation bank 0 000h general p urpo se a rea ram bank 0 system r egister 080h~0ffh of bank 0 store system registers (128 bytes). bank 0 type instructions (e.g. b0mov, b0add, b0bts1, b0bset ) to control bank 0 ram in non - zero ram bank condition directly. 2.2.1 system register 2.2.1.1 system register table 0 1 2 3 4 5 6 7 8 9 a b c d e f 8 l h r z y - pflag - - - - - - - - - 9 - - - - - - - - - - cmdb0 cmdb1 cm0m c m1m cm2m opm a - - - - - - - - - - - - - - p4con - b - adm adb adr adt - - - p0m - - - - - - pedge c p1w p1m - - p4m - - - intrq inten oscm - wdtr tc0r pcl pch d p0 p1 - - p4 - - - t0m t0c tc0m tc0c bzm - - stkp e p0ur p1ur - - p4ur - @hl @yz tc0d - - - - - - - f stk7l stk7h stk6l stk6h stk5l stk5h stk4l stk4h stk3l stk3h stk2l stk2h stk1l stk1h stk0l stk0h 2.2.1.2 system register description h, l = working, @ hl addressing register. y, z = working, @yz and rom addressing register. r = working register an d rom look - up data buffer. pflag = s pecial flag register. cmdb0 = c o mparator output de - bounce control register 0. cmdb1 = c o mparator output de - bounce control register 1. cm0m = comparator 0 mode register. cm1m = comparator 1 mode register. cm2m = compa rator 2 mode register. opm = op amp 0~2 mode register. p4con = p4 configuration register. adm = adc mode register. adb = adc data buffer. adr = adc resolution select register. adt = adc offset calibration register. pedge = p0.0, p0.1, p0.2 edge directi on register. intrq = interrupt request register. inten = interrupt enable register. oscm = oscillator mode register. wdtr = watchdog timer clear register. pnm = port n input/output mode register. pn = port n data buffer. pnur = port n pull - up resister control register. pch, pcl = program counter. t0m = t0 mode register. t0c = t0 counting register. t c0 m = t c0 mode register. t c0 c = tc 0 counting register. tc0r = tc0 auto - reload data buffer. tc0d = tc0 duty control register. bzm = 2k/4k buzzer mode regi ster. @ hl = ram hl indirect addressing index pointer. @yz = ram yz indirect addressing index pointer. stkp = stack pointer buffer. stk0~stk 7 = stack 0 ~ stack 7 buffer.
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 23 version 1. 6 2.2.1.3 bit definition of system register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 b it0 r/w remarks 080h lbit7 lbit6 lbit5 lbit4 lbit3 lbit2 lbit1 lbit0 r/w l 081h hbit7 hbit6 hbit5 hbit4 hbit3 hbit2 hbit1 hbit0 r/w h 082h rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 r/w r 083h zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 r/w z 084h ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 r/w y 086h nt0 npd lvd36 lvd24 c dc z r/w pflag 09ah cm1d3 cm1d2 cm1d1 cm1d0 cm0d3 cm0d2 cm0d1 cm0d0 r/w cmdb0 09bh cm2d3 cm2d2 cm2d1 cm2d0 r/w cmdb1 09ch cm0en cm0oen cm0out cm0sf cm0g r/w cm0m 09dh cm1en cm1oen cm1out cm1sf cm1g cm2rs2 cm2rs1 cm2rs0 r/w cm1m 09eh cm2en cm2oen cm2out cm2sf cm2g cm2rs2 cm2rs1 cm2rs0 r/w cm2m 09fh open r/w opm 0aeh p4con7 p4con6 p4con5 p4con4 p4con3 p4con2 p4con1 p4con0 w p4con 0b1h adenb ads eoc g chs avrefh chs2 chs1 chs0 r/w adm 0b2h adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 r adb 0b3h adcks1 adlen adcks0 adb3 adb2 adb1 adb0 r/w adr 0b4h adts1 adts0 adt4 adt3 adt2 adt1 adt0 r/w adt 0b8h p06m p05m - p03m p02m - p00m r/w p0m 0bfh p00g1 p00g0 r/w pedge 0c0h p16w p15w p14w p13w p12w p11w p10w w p1w 0c1h p16m p15m p14m p13m p12m p11m p10m r/w p1m 0c4h p47m p46m p45m p44m p43m p42m p41m p40m r/w p4m 0c8h adcirq tc0irq t0irq cm2irq cm1irq cm0irq p00irq r/w intrq 0c9h adcien tc0ien t 0ien cm2ien cm1ien cm0ien p00ien r/w inten 0cah cpum1 cpum0 clkmd stphx r/w oscm 0cch wdtr7 wdtr6 wdtr5 wdtr4 wdtr3 wdtr2 wdtr1 wdtr0 w wdtr 0cdh tc0r7 tc0r6 tc0r5 tc0r4 tc0r3 tc0r2 tc0r1 tc0r0 w tc0r 0ceh pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 r/w pcl 0 cfh pc11 pc10 pc9 pc8 r/w pch 0d0h p06 p05 p04 p03 p02 p01 p00 r/w p0 0d1h p16 p15 p14 p13 p12 p11 p10 r/w p1 0d4h p47 p46 p45 p44 p43 p42 p41 p40 r/w p4 0d8h t0enb t0rate2 t0rate1 t0rate0 r/w t0m 0d9h t0c7 t0c6 t0c5 t0c4 t0c3 t0c2 t0c1 t0c0 r/w t0c 0dah tc0enb tc0rate2 tc0rate1 tc0rate0 tc0cks tc0dir tc0po pwm0ou t r/w tc0m 0dbh tc0c7 tc0c6 tc0c5 tc0c4 tc0c3 tc0c2 tc0c1 tc0c0 r/w tc0c 0dch bzen bzrate1 bzrate0 r/w bzm 0dfh gie stkpb2 stkpb1 stkpb0 r/w stkp 0e0h p06r p05r - p03r p02r - p00r w p0ur 0e1h p16r p15r p14r p13r p12r p11r p10r w p1ur 0e4h p47r p46r p45r p44r p43r p42r p41r p40r w p4ur 0e6h @hl7 @hl6 @hl5 @hl4 @hl3 @hl2 @hl1 @hl0 r/w @hl 0e7h @yz7 @yz6 @yz5 @yz4 @yz3 @yz2 @yz1 @yz0 r/w @yz 0e8h tc0d7 tc0d6 tc0d5 tc 0d4 tc0d3 tc0d2 tc0d1 tc0d0 r/w tc0d 0f0h s7pc7 s7pc6 s7pc5 s7pc4 s7pc3 s7pc2 s7pc1 s7pc0 r/w stk7l 0f1h s7pc11 s7pc10 s7pc9 s7pc8 r/w stk7h 0f2h s6pc7 s6pc6 s6pc5 s6pc4 s6pc3 s6pc2 s6pc1 s6pc0 r/w stk6l 0f3h s6pc11 s6pc10 s6pc9 s6pc8 r/w stk6h 0f4h s5pc7 s5pc6 s5pc5 s5pc4 s5pc3 s5pc2 s5pc1 s5pc0 r/w stk5l 0f5h s5pc11 s5pc10 s5pc9 s5pc8 r/w stk5h 0f6h s4pc7 s4pc6 s4pc5 s4pc4 s4pc3 s4pc2 s4pc1 s4pc0 r/w stk4l 0f7h s4pc11 s4pc10 s4pc9 s4pc8 r/w stk4h 0f8h s3pc7 s3pc6 s3pc5 s3pc4 s3pc3 s3pc2 s3pc1 s3pc0 r/w stk3l 0f9h s3pc11 s3pc10 s3pc9 s3pc8 r/w stk3h 0fah s2pc7 s2pc6 s2pc5 s2pc4 s2pc3 s2pc2 s2pc1 s2pc0 r/w stk2l 0fbh s2pc11 s2pc10 s2pc9 s2pc8 r/w stk2h 0fch s1pc7 s1pc6 s1pc5 s1pc4 s1pc3 s1pc2 s1pc1 s1pc0 r/w stk1l 0fdh s1pc11 s1pc10 s1pc9 s1pc8 r/w stk1h
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 24 version 1. 6 0feh s0pc7 s0pc6 s0pc5 s0pc4 s0pc3 s0pc2 s0pc1 s0pc0 r/w stk0l 0ffh s0pc11 s0pc10 s0pc9 s0pc8 r/w stk0h ? note: 1. to avoid system error, make sure to put all the 0 and 1 as it indicates in the above table . 2. a ll of register name s had been declared in sn8asm assembler. 3. one - bit name had been declared in sn8asm assembler with f prefix code. 4. b0bset, b0bclr, bset, bclr instructions are only available to the r/w registers .
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 25 version 1. 6 2.2.2 accumulator the acc is an 8 - bit data register responsible for transferring or manipulating data between alu and data memory. if the result of operating is zero (z) or there is carry (c or dc) occurrence, then these flags will be set to pflag register. acc is not in data memory (ram) , so acc can?t be access by b0mov instruction during the instant addressing mode. ? example: read and write acc value. ; read acc data and store in buf data memory . mov buf, a ; write a immediate data into acc . mov a, #0fh ; write acc data from buf data memory . mov a, buf ; or b0 mov a, buf the system doesn?t store acc and pflag value when interrupt executed. acc and pflag data must be saved to other data memories. push , pop save and load acc, pflag data into buff ers. ? example: protect acc and working registers . int_service: push ; save acc and pflag to buffers. pop ; l oad acc and pflag from buffers. reti ; exit interrupt service vector
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 26 version 1. 6 2.2.3 program flag the pflag register con tains the arithmetic status of alu operation, system reset status and lvd detecting status. nt0, npd bits indicate system reset status including power on reset, lvd reset, reset by external pin active and watchdog reset. c, dc, z bits indicate the result s tatus of alu operation. lvd24, lvd36 bits indicate lvd detecting power voltage status. 086h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pflag nt0 npd lvd36 lvd24 - c dc z read/write r/w r/w r r - r/w r/w r/w after reset - - 0 0 - 0 0 0 bit [7:6] nt0, npd: reset status flag. nt0 npd reset status 0 0 watch - dog time out 0 1 reserved 1 0 reset by lvd 1 1 reset by external reset pin bit 5 lvd36: lvd 3.6v operating flag and only support lvd code option is lvd_h. 0 = inactive (vdd > 3.6v). 1 = act ive (vdd Q 3.6v). bit 4 lvd24: lvd 2.4v operating flag and only support lvd code option is lvd_m. 0 = inactive (vdd > 2.4v). 1 = active (vdd Q 2.4v). bit 2 c: carry flag 1 = a ddition with carry , subtraction without borrowing , rotation with shifting out l ogic 1 , comparison result R 0. 0 = a ddition without carry , subtraction with borrowing signal , rotation with shifting out logic 0 , comparison result < 0. bit 1 dc: decimal carry flag 1 = a ddition with carry from low nibble , subtraction without borrow f rom high nibble. 0 = a ddition without carry from low nibble , subtraction with borrow from high nibble. bit 0 z: zero flag 1 = the result of an a rithmetic /logic/branch operation is zero . 0 = the result of an a rithmetic /logic/branch operation is not zero . ? note: refer to instruction set table for detailed information of c, dc and z flags.
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 27 version 1. 6 2.2.4 program counter the program counter (pc) is a 1 2 - bit binary counter separated into the high - byte 4 and the low - byte 8 bits. this counter is responsible for pointin g a location in order to fetch an instruction for kernel circuit. normally, the program counter is automatically incremented with each instruction during program execution. besides, it can be replaced with specific address by executing call or jmp instru ction. when jmp or call instruction is executed, the destination address will be inserted to bit 0 ~ bit 11 . bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pc - - - - pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 after reset - - - - 0 0 0 0 0 0 0 0 0 0 0 0 pch pcl ? one address skipping there are nine instructions (cmprs, incs, incms, decs, decms, bts0, bts1, b0bts0, b0bts1) with one address skipping function. if the result of these instr uctions is true, the pc will add 2 steps to skip next instruction. if the condition of bit test instruction is true, the pc will add 2 steps to skip next instruction. b0bts1 fc ; to skip, if carry_flag = 1 jmp c0step ; else jump to c0step. b0bts 0 f z ; to skip, if zero flag = 0. jmp c1step ; else jump to c1step. if the acc is equal to the immediate data or memory, the pc will add 2 steps to skip next instruction. cmprs a, #12h ; to skip, if acc = 12h. jmp c0step ; else jump to c0step.
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 28 version 1. 6 if the destination increased by 1 , which results overflow of 0xff to 0x00, the pc will add 2 steps to skip next instruction. incs in struction: incs buf0 jmp c0step ; jump to c0step if acc is not zero. c0step: nop incms instruction: incms buf0 jmp c0step ; jump to c0step if buf0 is not zero. c0step: nop if the destination decreased by 1 , which results underflow of 0x0 1 to 0x 00 , the pc will add 2 steps to skip next instruction. decs instruction: decs buf0 jmp c0step ; jump to c0step if acc is not zero. c0step: nop decms instruction: decms buf0 jmp c0step ; jump to c0st ep if buf0 is not zero. c0step: nop
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 29 version 1. 6 ? multi - address jumping users can jump a round the multi - address by either jmp instruction or add m, a instruction (m = pcl) to activate multi - address jumping function. program counter supports add m,a , adc m,a and b0add m,a instructions for carry to pch when pcl overflow automatically. for jump table or others applications, users can calculate pc value by the three instructions and don?t care pcl overflow problem. ? note : pch only support pc up cou nting result and doesn t support pc down counting. when pcl is carry after pcl+acc, pch adds one automatically. if pcl borrow after pcl C acc, pch keeps value and not change. ? example: if pc = 0323h (pch = 03h , pcl = 23h) ; pc = 0323h mov a, #28h b0mov pcl, a ; jump to address 0328h ; pc = 0328h mov a, #00h b0mov pcl, a ; jump to address 0300h ? example: if pc = 0323h (pch = 03h , pcl = 23h) ; pc = 0323h b0add pcl, a ; pcl = pcl + acc, the pch cannot be changed. jmp a0point ; if acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 30 version 1. 6 2.2.5 h, l registers the h and l registers are the 8 - bit buffers. there are tw o major functions of these registers. ? c an be used as general working registers ? c an be used as ram data pointers with @hl register 081h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 h hbit7 hbit6 hbit5 hbit4 hbit3 hbit2 hbit1 hbit0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset - - - - - - - - 080h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 l lbit7 lbit6 lbit5 lbit4 lbit3 lbit2 lbit1 lbit0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset - - - - - - - - ? example: if want to read a data from ram address 20h of bank_0, it can use indirectly addressing mode to access data as following. b0mov h, #00h ; to set ram bank 0 for h register b0mov l, #20h ; to set location 20h for l register b0mov a, @hl ; to read a data into acc ? example: clear general - purpose data memory area of bank 0 using @hl register. clr h ; h = 0, bank 0 b0mov l, #07fh ; l = 7fh, the last address of the data memory area clr_hl_buf: clr @hl ; clear @hl to be zero decms l ; l C
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 31 version 1. 6 2.2.6 y, z registers the y and z registers are the 8 - bit buffers. there are three major functions of these register s. ? c an be used as general working registers ? c an be used as ram data pointers with @yz register ? c an be used as rom data pointer with the movc instruction for look - up table 084h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 y ybit7 ybit6 ybit5 ybit4 ybi t3 ybit2 ybit1 ybit0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset - - - - - - - - 083h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 z zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset - - - - - - - - ? example: uses y, z register as the data pointer to access data in the ram address 025h of bank0. b0mov y, #00h ; to set ram bank 0 for y register b0mov z, #25h ; to set location 25h for z register b0mov a, @yz ; to read a data int o acc ? example: uses the y, z register as data pointer to clear the ram data. b0mov y, #0 ; y = 0, bank 0 b0mov z, #07fh ; z = 7fh, the last address of the data memory area clr_yz_buf: clr @yz ; clear @yz to be zero decms z ; z C 2.2.7 r register r register is an 8 - bit buffer. there are two major functions of the register. ? can be used a s working register ? for store high - byte data of look - up table (movc instruction executed, the high - byte data of specified rom address will be stored in r register and the low - byte data will be stored in acc). 082h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset - - - - - - - - ? note: please refer to the look - up table description about r register look - up table application.
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 32 version 1. 6 2.3 addressing mode 2.3.1 i mmediate addressing mode the immediate addressing mode uses an immediate data to set up the location in acc or specific ram. ? example: move the immediate data 12h to acc. mov a, #12h ; to set an immediate data 12h into acc. ? example: move the immedi ate data 12h to r register. b0mov r, #12h ; to set an immediate data 12h into r register. ? note: in immediate addressing mode application, the specific ram must be 0x80~0x87 working register. 2.3.2 directly addressing mode the directly addressing mode moves the content of ram location in or out of acc. ? example: move 0x12 ram location data into acc. b0mov a, 12h ; to get a content of ram location 0x12 of bank 0 and save in acc. ? example: move acc data into 0x12 ram location. b0mov 12h, a ; to ge t a content of acc and save in ram location 12h of bank 0. 2.3.3 indirectly addressing mode the indirectly addressing mode is to access the memory by the data pointer registers (h/l, y/z). ? example: indirectly addressing mode with @hl register b0mov h, #0 ; to clear h register to access ram bank 0. b0mov l, #12h ; to set an immediate data 12h into l register. b0mov a, @hl ; use data pointer @hl reads a data from ram location ; 012h into acc. ? example: indirectly addressing mode with @yz register b0mov y, #0 ; to clear y register to access ram bank 0. b0mov z, #12h ; to set an immediate data 12h into z register. b0mov a, @yz ; use data pointer @yz reads a data from ram location ; 012h into acc.
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 33 version 1. 6 2.4 stack operation 2.4.1 overview the stack buf fer has 8 - level. these buffers are designed to push and pop up program counter?s (pc) data when interrupt service routine and call instruction are executed. the stkp register is a pointer designed to point active level in order to push or pop up data fro m stack buffer. the stknh and stknl are the stack buffer s to store program counter (pc) data. ret / reti call / interrupt stkp = 7 stkp = 6 stkp = 5 stkp = 4 stack level stk7h stk6h stk5h stk4h stack buffer high byte pch stkp stk7l stk6l stk5l stk4l stack buffer low byte pcl stkp stkp - 1 stkp + 1 stkp = 3 stkp = 2 stkp = 1 stkp = 0 stk3l stk2l stk1l stk0l stk3h stk2h stk1h stk0h
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 34 version 1. 6 2.4.2 stack registers the stack pointer (stkp) is a 3 - bit register to store the address used to access the stack buffer, 13 - bit data memory ( stknh and stknl ) set aside for temporary storage of stack addresses. the two stack operations are writing to the top of the stack (push) and reading from the top of stack (pop). push operation decrements the stkp and the pop operation incre ments each time. that makes the stkp always point to the top address of stack buffer and write the last program counter value (pc) into the stack buffer. the program counter (pc) value is stored in the stack buffer before a call instruction executed or during interrupt service routine. stack operation is a lifo type (last in and first out). the stack pointer (stkp) and stack buffer (stknh and stknl) are located in the system register area bank 0. 0dfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stkp gi e - - - - stkpb2 stkpb1 stkpb0 read/write r/w - - - - r/w r/w r/w after reset 0 - - - - 1 1 1 bit[2:0] stkpbn: stack pointer (n = 0 ~ 2) bit 7 gie: global interrupt control bit. 0 = d isable. 1 = e nable. please refer to the interrupt chapter. ? exa mple: stack pointer (stkp) reset, we strongly recommended to clear the stack pointers in the beginning of the program. mov a, #0000 0 111b b0mov stkp, a 0f0h~0ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stknh - - - snpc12 snpc11 snpc10 sn pc9 snpc8 read/write - - - r/w r/w r/w r/w r/w after reset - - - 0 0 0 0 0 0f0h~0ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stknl snpc7 snpc6 snpc5 snpc4 snpc3 snpc2 snpc1 snpc0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 stkn = stknh , stknl (n = 7 ~ 0)
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 35 version 1. 6 2.4.3 stack operation example the two kinds of stack - save operations refer to the stack pointer (stkp) and write the content of program counter (pc) to the stack buffer are call instruction and interrupt service. u nder each condition, the stkp decre ases and points to the next available stack location. the stack buffer stores the program counter about the op - code address. the stack - save operation is as the following table. stack level stkp register stack buffer des cription stkpb 2 stkpb 1 stkpb0 high byte low byte 0 1 1 1 free free - 1 1 1 0 stk0h stk0l - 2 1 0 1 stk1h stk1l - 3 1 0 0 stk2h stk2l - 4 0 1 1 stk3h stk3l - 5 0 1 0 stk4h stk4l - 6 0 0 1 stk5h stk5l - 7 0 0 0 stk6h stk6l - 8 1 1 1 stk7h stk7l - > 8 1 1 0 - - stack over, error there are stack - restore operation s correspond to e ach push operation to restore the program counter (pc). the reti instruction uses for interrupt service routine. the ret instruction is for call instruction. when a pop operation occurs, the stkp is incre mented and points to the next free stack location. the stack buffer restores the last program counter (pc) to the program counter registers. the stack - restore operation is as the following table. stack level stkp registe r stack buffer description stkpb2 stkpb1 stkpb0 high byte low byte 8 1 1 1 stk7h stk7l - 7 0 0 0 stk6h stk6l - 6 0 0 1 stk5h stk5l - 5 0 1 0 stk4h stk4l - 4 0 1 1 stk3h stk3l - 3 1 0 0 stk2h stk2l - 2 1 0 1 stk1h stk1l - 1 1 1 0 stk0h stk0l - 0 1 1 1 free free -
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 36 version 1. 6 2.5 code option table the code option is the system hardware configurations including oscillator type, watchdog timer operation, lvd option, reset pin option and otp rom security control. the code option items are as following table: code option content function description high_clk ihrc_16m high speed internal 16mhz rc. xin/xout pins are bi - direction gpio mode. rc low cost rc for external high clock oscillator. xin pin is connected to rc oscillator. xout pin is bi - direction gpio m ode. 32k x?tal 12m x?tal 4m x?tal 2.5.1 fcpu code option fcpu means instruction cycle of normal mode (high clock). in slow mo de, the system clock source is internal low speed rc oscillator. the fcpu of slow mode isn ? t controlled by fcpu code option and fixed flosc/4 (16khz/4 @3v, 32khz/4 @5v). 2.5.2 reset_pin code option the reset pin is shared with general input only pin controlled by code option. ? reset : the reset pin is external reset function . w hen falling edge trigger occurring, the system will be reset. ? p04 : set reset pin to general input only pin (p0.4). the external reset function is disabled and the pin is input pin. 2.5.3 secur ity code option security code option is otp rom protection. when enable security code option, the rom code is secured and not dumped complete rom contents.
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 37 version 1. 6 3 3 3 reset 3.1 overview the system would be reset in three conditions as following. ? power on reset ? wa tchdog reset ? brown out reset ? external reset (only supports external reset pin enable situation) when any reset condition occurs, all system registers keep initial status, program stops and program counter is cleared. after reset status released, the syst em boots up and program starts to execute from org 0. the nt0, npd flags indicate system reset status. the system can depend on nt0, npd status and go to different paths by program. 086h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pflag nt0 npd lvd36 lvd24 - c dc z read/write r/w r/w r r - r/w r/w r/w after reset - - 0 0 - 0 0 0 bit [7:6] nt0, npd: reset status flag. nt0 npd condition description 0 0 watchdog reset watchdog timer overflow. 0 1 reserved - 1 0 power on reset and lvd reset. power voltage is lower than lvd detecting level. 1 1 external reset external reset pin detect low level status. finishing any reset sequence needs some time. the system provides complete procedure s to make the power on reset successful. for different oscillat or types, the reset time is different. that causes the vdd rise rate and start - up time of different oscillator is not fixed. rc type oscillator ? s start - up time is very short, but the crystal type is longer. under client terminal application, users have to take care the power on reset time for the master terminal requirement. the reset timing diagram is as following. vdd vss vdd vss watchdog normal run watchdog stop system normal run system stop lvd detect level external reset low detect external reset high detect watchdog overflow watchdog reset delay time external reset delay time power on delay time power external reset watchdog reset system status
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 38 version 1. 6 3.2 power on reset the power on reset depend no lvd operation for most power - up situations. the power supplying to system is a rising curve and needs some time to achieve the normal voltage. power on reset sequence is as following. ? power - up: system detects the power voltage up and waits for power stable. ? external reset (only external reset pin enable): system check s external reset pin status. if external reset pin is not high level, the system keeps reset status and waits external reset pin released. ? system initialization: all system registers is set as initial conditions and system is ready. ? oscillator warm up: os cillator operation is successfully and supply to system clock. ? program executing: power on sequence is finished and program executes from org 0. 3.3 watchdog reset watchdog reset is a system protection. in normal condition, system works well and clear s watc hdog timer by program. under error condition, system is in unknown situation and watchdog can ? t be clear by program before watchdog timer overflow. watchdog timer overflow occurs and the system is reset. after watchdog reset, the system restarts and return s normal mode. watchdog reset sequence is as following. ? watchdog timer status: system checks watchdog timer overflow status. if watchdog timer overflow occurs, the system is reset. ? system initialization: all system registers is set as initial conditions a nd system is ready. ? oscillator warm up: oscillator operation is successfully and supply to system clock. ? program executing: power on sequence is finished and program executes from org 0. watchdog timer application note is as following. ? before clearin g watchdog timer, check i/o status and check ram contents can improve system error. ? don?t clear watchdog timer in interrupt vector and interrupt service routine. that can improve main routine fail. ? clearing watchdog timer program is only at one part of the program. this way is the best structure to enhance the watchdog timer function. ? note: please refer to the watchdog timer about watchdog timer detail information . 3.4 brown out reset the brown out reset is a power dropping condition. the power drops fro m normal voltage to low voltage by external factors (e.g. eft interference or external loading changed). the brown out reset would make the system not work well or executing program error. brown out reset diagram vdd vss v1 v2 v3 system work well area system work error area
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 39 version 1. 6 the power dropping might through the voltage range that ? s the system dead - band. the dead - band means the power range can?t offer the system minimum operation power requirement . the above diagram is a typical brown out reset diagram . there is a serious noise under the vdd, and vdd voltage drops very deep. there is a dotted line to separate the system working area. the above area is the system work well area. the below area is the system work error area called dead - band. v1 does n?t touch the below area and not effect th e system operation. but the v2 and v3 is under the below area and may induce the system error occurrence. let system under dead - band includes some condition s. dc application: the power source of dc application is usually using battery. when low battery co ndition and mcu drive any loading, the power drops and keeps in dead - band. under the situation, the power won?t drop deeper and not touch the system reset voltage. that make s the system under dead - band. ac application: in ac power application, the dc powe r is regulated from ac power source. this kind of power usually couples with ac noise that makes the dc power dirty. or the external loading is very heavy, e.g. driving motor. the loading operating induces noise and overlaps with the dc power. vdd drops by the noise, and the system works under unstable power situation. the power on duration and power down duration are longer in ac application. the system power on sequence protects the power on successful, but the power down situation is like dc low battery condition. when turn off the ac power, the vdd drops slowly and through the dead - band for a while. 3.5 the system operating voltage to improve the brown out reset needs to know the system minimum operating voltage which is depend on the system executing rate and power level. different system executing rates have different system minimum operating voltage. the electrical characteristic section shows the system voltage to executing rate relationship . normally the system operation voltage area is higher than the system reset voltage to vdd, and the reset voltage is decided by lvd detect level. the system minimum operating voltage rises when the system executing rate upper even higher than system reset voltage. the dead - band definiti on is the system minimum operating voltage above the system reset voltage. 3.6 low voltage detector (lvd) vdd (v) system rate (fcpu) system mini. operating voltage. system reset voltage. dead-band area normal operating area reset area vdd vss system normal run system stop lvd detect voltage power on delay time power system status power is below lvd detect voltage and system reset.
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 40 version 1. 6 the lvd (low voltage detector) is built - in sonix 8 - bit mcu to be brown out reset protection. when the vdd drops and is be low lvd detect voltage, the lvd would be triggered, and the system is reset. the lvd detect level is different by each mcu. the lvd voltage level is a point of voltage and not easy to cover all dead - band range. using lvd to improve brown out reset is depen d on application requirement and environment . if the power variation is very deep, violent and trigger the lvd, the lvd can be the protection. if the power variation can touch the lvd detect level and make system work error, the lvd can ? t be the protection and need to other reset methods. more detail lvd information is in the electrical characteristic section. the lvd is three levels design (2.0v/2.4v/3.6v) and controlled by lvd code option. the 2.0v lvd is always enable for power on reset and brown out re set. the 2.4v lvd includes lvd reset function and flag function to indicate vdd status function . the 3.6v includes flag function to indicate vdd status. lvd flag function can be an easy low battery detector . lvd24, lvd36 flags indicate vdd voltage level. f or low battery detect application, only checking lvd24, lvd36 status to be battery status. this is a cheap and easy solution. 086h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pflag nt0 npd lvd36 lvd24 - c dc z read/write r/w r/w r r - r/w r/w r/w a fter reset - - 0 0 - 0 0 0 bit 5 lvd36: lvd 3.6v operating flag and only support lvd code option is lvd_h. 0 = inactive (vdd > 3.6v). 1 = active (vdd Q 3.6v). bit 4 lvd24: lvd 2.4v operating flag and only support lvd code option is lvd_m. 0 = inactive (vdd > 2.4v). 1 = active (vdd Q 2.4v). lvd lvd code option lvd_l lvd_m lvd_h lvd_max 2.0v reset available available available available 2 .4v flag - available - - 2.4v reset - - available - 3.6v flag - - available - 3.6v reset - - - available lvd_l if vdd < 2.0v, system will be reset. disable lvd24 and lvd36 bit of pflag register. lvd_m if vdd < 2.0v, system will be reset. enable lvd24 bit of pflag register. if vdd > 2.4v, lvd24 is 0. if vdd Q 2.4v, lvd24 flag is 1. disable lvd36 bit of pflag register. lvd_h if vdd < 2.4v, system will be reset. enable lvd24 bit of pflag register. if vdd > 2.4v, lvd24 is 0. if vdd Q 2.4v, lvd24 flag is 1. enable lvd36 bit of pflag register. if vdd > 3.6v, lvd36 is 0. if vdd Q 3.6v, lvd36 flag is 1. lvd_max if vdd < 3.6v, system will be reset. ? note: 1. after any lvd reset, lvd24, lvd36 flags are cleared. 2. the voltage level of lvd 2.4v or 3.6v is for design reference only. don t use the lvd indicator as pr ecision vdd measurement.
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 41 version 1. 6 3.7 brown out reset impr ovement how to improve the brown reset condition? there are some methods to improve brown out reset as following. ? lvd reset ? watchdog reset ? reduce the system executing rate ? external reset circuit. (zener di ode reset circuit, voltage bias reset circuit, external reset ic) ? note: 1. the zener diode reset circuit , voltage bias reset circuit and external reset ic can completely improve the brown out reset, dc low battery and ac slow power down condition s. 2. for ac power application and enhance eft performance, the system clock is 4mhz/4 (1 mips) and use external reset ( zener diode reset circuit , voltage bias reset circuit , external reset ic ). the structure can improve noise effective and get good eft c haracteristic. watchdog reset: the watchdog timer is a protection to make sure the system executes well. normally the watchdog timer would be clear at one point of program. don?t clear the watchdog timer in several addresses. the system executes norma lly and the watchdog won ? t reset system. when the system is under dead - band and the execution error, the watchdog timer can?t be clear by program. the watchdog is continuously counting until overflow occurrence. the overflow signal of watchdog timer trigge rs the system to reset, and the system return to normal mode after reset sequence. this method also can improve brown out reset condition and make sure the system to return normal mode. if the system reset by watchdog and the power is still in dead - band, the system reset sequence won?t be successful and the system stays in reset status until the power return to normal range. watchdog timer application note is as following. reduce the system executing rate: if the system rate is fast and the dead - band exis ts, to reduce the system executing rate can improve the dead - band. the lower system rate is with lower minimum operating voltage. select the power voltage that ? s no dead - band issue and find out the mapping system rate. adjust the system rate to the value a nd the system exits the dead - band issue. this way needs to modify whole program timing to fit the application requirement. external reset circuit: the external reset methods also can improve brown out reset and is the complete solution. there are three ex ternal reset circuits to improve brown out reset including zener diode reset circuit , voltage bias reset circuit and external reset ic . these three reset structures use external reset signal and control to make sure the mcu be reset under power dropp ing and under dead - band. the external reset information is describe d in the next section.
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 42 version 1. 6 3.8 external reset external reset function is controlled by reset_pin code option. set the code option as reset option to enable external reset function. external r eset pin is schmitt trigger structure and low level active. the system is running when reset pin is high level voltage input. the reset pin receives the low voltage and the system is reset. the external reset operation actives in power on and normal runnin g mode. during system power - up, the external reset pin must be high level input, or the system keeps in reset status. external reset sequence is as following. ? external reset (only external reset pin enable): system checks external reset pin status. if ext ernal reset pin is not high level, the system keeps reset status and waits external reset pin released. ? system initialization: all system registers is set as initial conditions and system is ready. ? oscillator warm up: oscillator operation is successfully and supply to system clock. ? program executing: power on sequence is finished and program executes from org 0. the external reset can reset the system during power on duration, and good external reset circuit can protect the system to avoid working at un usual power condition, e.g. brown out reset in ac power application 3.9 external reset circu it 3.9.1 simply rc reset circuit this is the basic reset circuit, and only includes r1 and c1. the rc circuit operation makes a slow rising si gnal into reset pin as power up. the reset signal is slower than vdd power up timing, and system occurs a power on signal from the timing difference. ? note: the reset circuit is no any protection against unusual power or brown out reset. mcu vdd vss vcc gnd r s t r1 47k ohm c1 0.1uf r2 100 ohm
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 43 version 1. 6 3.9.2 diode & rc reset circuit this is the better reset circuit. the r1 and c1 circuit operation is like the simply reset circuit to make a power on signal. the reset circuit has a simply protection against unusual power. the diode offers a po wer positive path to conduct higher power to vdd. it is can make reset pin voltage level to synchronize with vdd voltage. the structure can improve slight brown out reset condition. ? note: the r2 100 ohm resistor of simply reset circuit and diode & rc reset circuit is necessary to limit any current flowing into reset pin from external capacitor c in the e vent of reset pin breakdown due to electrostatic discharge (esd) or electrical over - stress (eos). 3.9.3 zener diode reset circuit the zener diode reset circuit is a simple low voltage detector and can improve brown out reset condition completely . use zener voltage to be the active level. when vdd voltage level is above vz + 0.7v , the c terminal of the pnp transistor outputs h igh voltage and mcu operates normally. when vdd is below vz + 0.7v , the c terminal of the pnp transistor outputs low voltage and mcu is in reset mode. decide the reset detect voltage by zener specification . select the right zener voltage to conform the a pplication. mcu vdd vss vcc gnd r s t r1 47k ohm c1 0.1uf diode r2 100 ohm mcu vdd vss vcc gnd r s t r1 33k ohm r3 40k ohm r2 10k ohm vz q1 e c b
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 44 version 1. 6 3.9.4 voltage bias reset circuit the voltage bias reset circuit is a low cost voltage detector and can improve brown out reset condition completely . the operating voltage is not accurate as zener diode reset circuit. us e r1, r2 bias voltage to be the active level. when vdd voltage level is above or equal to 0.7v x (r1 + r2) / r1 , the c terminal of the pnp transistor outputs high voltage and mcu operates normally. when vdd is below 0.7v x (r1 + r2) / r1 , the c termina l of the pnp transistor outputs low voltage and mcu is in reset mode. decide the reset detect voltage by r1, r2 resistances. select the right r1, r2 value to conform the application. in the circuit diagram condition, the mcu ? s reset pin level varies with vdd voltage variation , and the differential voltage is 0.7v. if the vdd drops and the voltage lower than reset pin detect level, the system would be reset. if want to make the reset active earlier, set the r2 > r1 and the cap between vdd and c terminal vol tage is larger than 0.7v. the external reset circuit is with a stable current through r1 and r2. for power consumption issue application, e.g. dc power system, the current must be consider ed to whole system power consumption. ? note: under unstable power c ondition as brown out reset, zener diode rest circuit and voltage bias reset circuit can protects system no any error occurrence as power dropping. when power drops below the reset detect voltage, the system reset would be triggered, and then system ex ecutes reset sequence. that makes sure the system work well under unstable power situation. 3.9.5 external reset ic the external reset circuit also use external reset ic to enhance mcu reset performance. this is a high cost and go od effect solution. by different application and system requirement to select suitable reset ic. the reset circuit can improve all power variation . mcu vdd vss vcc gnd r s t r1 47k ohm r3 2k ohm r2 10k ohm q1 e c b mcu vdd vss vcc gnd r s t reset ic vdd vss rst bypass capacitor 0.1uf
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 45 version 1. 6 4 4 4 system clock 4.1 overview the micro - controller is a dual clock system including high - speed and low - speed cloc ks. the high - speed clock includes internal high - speed oscillator and external oscillators selected by high_clk code option. the low - speed clock is from internal low - speed oscillator controlled by clkmd bit of oscm register. both high - speed clock and lo w - speed clock can be system clock source through a divider to decide the system clock rate. ? high - speed oscillator internal high - speed oscillator is 16mhz rc type called ihrc . external high - speed oscillator includes crystal/ ceramic (4mhz, 12mhz, 32khz) and rc type. ? low - speed oscillator internal low - speed oscillator is 16khz @3v, 32khz @5v rc type called ilrc . ? system clock block diagram ? hosc: high_clk code option. ? fhosc: external high - speed clock / internal high - speed rc clock. ? flosc: internal low - speed rc clock (about 16khz@3v and @5v) . ? fosc: system clock source. ? fcpu: instruction cycle. 4.2 fcpu (instruction cy cle) the system clock rate is instruction cycle called fcpu which is divided from the system clock source and decides the system operating rate. fcpu rate is selected by fcpu code option and the range is fhosc/ 4 ~fhosc/1 6 under system normal mode. if the system high clock source is external 4mhz crystal, and the fcpu code option is fhosc/4, the fcpu frequency is 4m hz/4 = 1mhz. under system slow mode, the fcpu is fixed flosc/4, 16khz/4=4khz @3v, 32khz/4=8khz @5v. 4.3 system high - speed clock the system high - speed clock has internal and external two - type. the external high - speed clock includes 4mhz, 12mhz, 32khz crystal / ceramic and rc type. these high - speed oscillators are selected by high_clk code option. f h o s c . f c p u = f h o s c / 4 ~ f h o s c / 1 6 f l o s c . f c p u = f l o s c / 4 c p u m [ 1 : 0 ] x i n x o u t s t p h x h o s c f c p u c o d e o p t i o n f o s c f o s c c l k m d f c p u
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 46 version 1. 6 4.3.1 high_clk code option for difference clock functions, sonix provides multi - type system high clock options controlled by high_clk code option. the high_clk code o ption defines the system oscillator types including ihrc_16m, rc, 32k x ? tal, 12m x ? tal and 4m x ? tal. these oscillator options support different bandwidth oscillator. ? ihrc_ 16 m: the system high - speed clock source is internal high - speed 16mhz rc type oscill ator. in the mode, xin and xout pins are bi - direction gpio mode, and not to connect any external oscillator device. ? rc: the system high - speed clock source is external low cost rc type oscillator. the rc oscillator circuit only connects to xin pin, and the xout pin is bi - direction gpio mode. ? 32k x tal: the system high - speed clock source is external low - speed 32768hz crystal. the option only supports 32768hz crystal and the rtc function is workable. ? 12m x tal: the system high - speed clock source is external high - speed crystal/ceramic. the oscillator bandwidth is 10mhz~16mhz. ? 4m x tal: the system high - speed clock source is external high - speed crystal/resonator. the oscillator bandwidth is 1mhz~10mhz. 4.3.2 internal high - speed oscillator rc type (ihrc) the inter nal high - speed oscillator is 16mhz rc type. the accuracy is 2% under commercial condition. when the high_clk code option is ihrc_16m , the internal high - speed oscillator is enabled. ? ihrc_16m: the system high - speed clock is internal 16mhz oscillator rc type. xin/xout pins are general purpose i/o pins. 4.3.3 external high - speed oscillator the external high - speed oscillator includes 4mhz, 12mhz, 32khz and rc type. the 4mhz, 12mhz and 32khz oscillators support crystal and ceramic types connected to xin/xout p ins with 20pf capacitors to ground. the rc type is a low cost rc circuit only connected to xin pin. the capacitance is not below 100pf , and use the resistance to decide the frequency. 4.3.4 external oscillator application circuit crystal/ceramic rc type ? note: connect the crystal/ceramic and c as near as possible to the xin/xout/vss pins of micro - controller. connect the r and c as near as possible to the vdd pin of micro - controller. mcu vcc gnd c 20pf xin x o u t vdd v s s c 20pf crystal r mcu vcc gnd xin x o u t v d d vss c
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 47 version 1. 6 4.4 system low - speed clock the system low clock source is the internal low - speed oscillator built in the micro - controller. t he low - speed oscillator uses rc type oscillator circuit. the frequency is affected by the voltage and temperature of the system. in common conditi on, the frequency of the rc oscillator is about 16khz at 3v and 32khz at 5v . the relation between the rc frequency and voltage is as the following figure . the internal low rc supports watchdog clock source and system slow mode controlled by clkmd bi t of oscm register. ? flosc = internal low rc oscillator (about 16khz @3v, 32khz @5v) . ? slow mode fcpu = flosc / 4 there are two conditions to stop internal low rc. one is power down mode, and the other is green mode of 32k mode and watchdog disable. if sys tem is in 32k mode and watchdog disable, only 32k oscillator actives and system is under low power consumption. ? example: stop internal low - speed oscillator by power down mode. b0bset fcpum0 ; to stop external high - speed oscillator and internal low - sp eed ; oscillator called power down mode (sleep mode). ? note: the internal low - speed clock can t be turned off individually . it is controlled by cpum0, cpum1 (32k, watchdog disable) bits of oscm register. internal low rc frequency 7.52 10.64 14.72 16.00 17.24 18.88 22.24 25.96 29.20 32.52 35.40 38.08 40.80 0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 40.00 45.00 2.1 2.5 3 3.1 3.3 3.5 4 4.5 5 5.5 6 6.5 7 vdd (v) freq. (khz) ilrc
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 48 version 1. 6 4.5 oscm register the oscm register is a n oscillator control register. it control s oscillator status, system mode. 095h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 oscm 0 0 0 cpum1 cpum0 clkmd stphx 0 read/write - - - r/w r/w r/w r/w - after reset - - - 0 0 0 0 - bit 1 stphx: e xternal high - speed oscillator control bit. 0 = external high - speed oscillator f ree run . 1 = external high - speed oscillator f ree run s top. i nternal low - speed rc oscillator is still running. bit 2 clkmd: system high/low clock mode control bit. 0 = n ormal (dual) mode . system clock is high clock. 1 = s low mode. system clock is internal low clock. bit[4:3] cpum [1:0] : cpu operating mode control bit s . 00 = normal . 01 = sleep (power down) mode . 10 = green mode . 11 = reserved. stphx bit controls internal high sp eed rc type oscillator and external oscillator operations. when stphx=0 , the external oscillator or internal high speed rc type oscillator active. when stphx=1 , the external oscillator or internal high speed rc type oscillator are disabled. the stphx f unction is depend on different high clock options to do different controls. ? ihrc_ 16 m: stphx=1 disables internal high speed rc type oscillator. ? rc, 4m, 12m, 32k: stphx=1 disables external oscillator. 4.6 system clock measurement under design period, t he users can measure system clock speed by software instruction cycle (fcpu). this way is useful in rc mode. ? example: fcpu instruction cycle of external oscillator . b0bset p0m.0 ; set p0.0 to be output mode for outputting fcpu toggle signal. @@: b0bset p0.0 ; o utput fcpu toggle signal in low - speed clock mode. b0bclr p0.0 ; measure the fcpu frequency by oscilloscope . jmp @b ? note: do not measure the rc frequency directly from xin; the probe impendence will affect the rc frequency.
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 49 version 1. 6 4.7 system clock timing parameter symbol description typical hardware configuration time tcfg 2048*f ilrc 64ms @ f ilrc = 32khz 128ms @ f ilrc = 16khz oscillator start up time tost the start - up time is depended on oscillator?s material, factory and archi tecture. normally, the low - speed oscillator?s start - up time is lower than high - speed oscillator. the rc type oscillator?s start - up time is faster than crystal type oscillator. - oscillator warm - up time tosp oscillator warm - up time of reset condition . 2 048*f hosc (power on reset, lvd reset, watchdog reset, external reset pin active.) 64ms @ f hosc = 32khz 512us @ f hosc = 4mhz 128 us @ f hosc = 16 mhz oscillator warm - up time of power down mode wake - up condition . 2048*f hosc crystal/resonator type oscilla tor, e.g. 32768hz crystal, 4mhz crystal, 16mhz crystal 32 *f hosc rc type oscillator , e.g. external rc type oscillator, internal high - speed rc type oscillator. x ? tal: 64ms @ f hosc = 32khz 512us @ f hosc = 4mhz 128 us @ f hosc = 16 mhz rc: 8u s @ f hosc = 4m hz 2 u s @ f hosc = 16m hz ? power on reset timing ? external reset pin reset timing v d d p o w e r o n r e s e t f l a g o s c i l l a t o r f c p u ( i n s t r u c t i o n c y c l e ) t c f g t o s t t o s p v p e x t e r n a l r e s e t p i n o s c i l l a t o r f c p u ( i n s t r u c t i o n c y c l e ) t c f g t o s t t o s p r e s e t p i n f a l l i n g e d g e t r i g g e r s y s t e m r e s e t . r e s e t p i n r e t u r n s t o h i g h s t a t u s . s y s t e m i s u n d e r r e s e t s t a t u s . e x t e r n a l r e s e t f l a g
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 50 version 1. 6 ? watchdog reset timing ? power down mode wake - up timing ? green mode wake - up timing w a t c h d o g r e s e t f l a g o s c i l l a t o r f c p u ( i n s t r u c t i o n c y c l e ) t c f g t o s t t o s p w a t c h d o g t i m e r o v e r f l o w . w a k e - u p p i n r i s i n g e d g e o s c i l l a t o r f c p u ( i n s t r u c t i o n c y c l e ) t o s p t o s t w a k e - u p p i n f a l l i n g e d g e s y s t e m i n s e r t s i n t o p o w e r d o w n m o d e . e d g e t r i g g e r s y s t e m w a k e - u p . w a k e - u p p i n r i s i n g e d g e o s c i l l a t o r f c p u ( i n s t r u c t i o n c y c l e ) w a k e - u p p i n f a l l i n g e d g e s y s t e m i n s e r t s i n t o g r e e n m o d e . e d g e t r i g g e r s y s t e m w a k e - u p . 0 x 0 0 0 x f f 0 x f e 0 x 0 1 0 x 0 2 . . . 0 x f d . . . . . . . . . . . . . . . t i m e r t i m e r o v e r f l o w .
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 51 version 1. 6 ? oscillator start - up time the start - up time is depended on oscillator?s material, fa ctory and architecture. normally, the low - speed oscillator?s start - up time is lower than high - speed oscillator. the rc type oscillator?s start - up time is faster than crystal type oscillator. l o w s p e e d c r y s t a l ( 3 2 k , 4 5 5 k ) t o s t c r y s t a l t o s t r c o s c i l l a t o r t o s t c e r a m i c / r e s o n a t o r t o s t
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 52 version 1. 6 5 5 5 system operation mode 5.1 overview the chip builds in four operating mode for difference clock rate and power saving reason. these modes control oscillators, op - code operation and analog peripheral devices ? operation. ? normal mode: system high - speed operating mode. ? slow mode: system low - s peed operating mode. ? p ower down mode : system power saving mode (sleep mode). ? green mode : system ideal mode. operating mode control block operating mode clock control table operating m ode normal mode slow mode green mode p ower down mode ehosc running by stphx by stphx stop ihrc running by stphx by stphx stop ilrc running running running stop cpu instruction executing executing stop stop t0 timer by t0enb by t0enb by t0enb inactive tc 0 timer by tc 0 enb by tc 0 enb by tc 0 e nb ( pwm active ) inactive w atchdog timer by watch_dog code option by watch_dog code option by watch_dog code option by watch_dog code option internal interrupt all active all active t0 all inactive external interrupt all active all active all active all inactive wakeup source - - p0, p1, t0 reset p0, p1 reset ? ehosc: external high - speed oscillator (xin/xout). ? i h rc: internal high - speed oscillator rc type. ? ilrc: internal low - speed oscillator rc type. p o w e r d o w n m o d e s l o w m o d e c l k m d = 1 c l k m d = 0 c p u m 1 , c p u m 0 = 0 1 . w a k e - u p c o n d i t i o n : p 0 , p 1 i n p u t s t a t u s i s l e v e l c h a n g i n g . t 0 t i m e r c o u n t e r i s o v e r f l o w . c p u m 1 , c p u m 0 = 1 0 . n o r m a l m o d e g r e e n m o d e w a k e - u p c o n d i t i o n : p 0 , p 1 i n p u t s t a t u s i s l e v e l c h a n g i n g . t 0 t i m e r c o u n t e r i s o v e r f l o w . w a k e - u p c o n d i t i o n : p 0 , p 1 i n p u t s t a t u s i s l e v e l c h a n g i n g . r e s e t c o n t r o l b l o c k o n e o f r e s e t t r i g g e r s o u r c e s a c t i v e s . o n e o f r e s e t t r i g g e r s o u r c e s a c t i v e s . o n e o f r e s e t t r i g g e r s o u r c e s a c t i v e s .
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 53 version 1. 6 5.2 normal mode the normal mode is system high c lock operating mode. the system clock source is from high speed oscillator. the program is executed. after power on and any reset trigger released, the system inserts into normal mode to execute program. when the system is wake - up from power down mode, the system also inserts into normal mode. in normal mode, the high speed oscillator actives, and the power consumption is largest of all operating modes. ? the program is executed, and full functions are controllable . ? the system rate is high speed. ? the high speed oscillator and internal low speed rc type oscillator active. ? normal mode can be switched to other operating modes through oscm register. ? power down mode is wake - up to normal mode. ? slow mode is switched to normal mode. ? green mode from normal mode is wake - up to normal mode. 5.3 slow mode the slow mode is system low clock operating mode. the system clock source is from internal low speed rc type oscillator. the slow mode is controlled by clkmd bit of oscm register. when clkmd=0, the system is in norma l mode. when clkmd=1, the system inserts into slow mode. the high speed oscillator won?t be disabled automatically after switching to slow mode, and must be disabled by spthx bit to reduce power consumption. in slow mode, the system rate is fixed flosc/4 ( flosc is internal low speed rc type oscillator frequency). ? the program is executed, and full functions are controllable . ? the system rate is low speed (flosc/4). ? the internal low speed rc type oscillator actives, and the high speed oscillator is control led by stphx=1. in slow mode, to stop high speed oscillator is strongly recommendation . ? slow mode can be switched to other operating modes through oscm register. ? power down mode from slow mode is wake - up to normal mode. ? normal mode is switched to slow m ode. ? green mode from slow mode is wake - up to slow mode. 5.4 power down mode the power down mode is the system ideal status. no program execution and oscillator operation. whole chip is under low power consumption status under 1ua. the power down mode is wak ed up by p0, p1 hardware level change trigger. p1 wake - up function is controlled by p1w register. any operating modes into power down mode, the system is waked up to normal mode. inserting power down mode is controlled by cpum0 bit of oscm register. w h en c pum0=1, the system inserts into power down mode. after system wake - up from power down mode, the cpum0 bit is disabled (zero status) automatically. ? the program stops executing, and full functions are disabled. ? all oscillators including external high spee d oscillator, internal high speed oscillator and internal low speed oscillator stop. ? the power consumption is under 1ua. ? the system inserts into normal mode after wake - up from power down mode. ? t h e power down mode wake - up source is p0 and p1 level change trigger. ? note: if the system is in normal mode, to set stphx=1 to disable the high clock oscillator. the system is under no system clock condition. this condition makes the system stay as power down mode, and can be wake - up by p0, p1 level change trigg er.
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 54 version 1. 6 5.5 green mode the green mode is another system ideal status not like power down mode. in power down mode, all functions and hardware devices are disabled. but in green mode, the system clock source keeps running, so the power consumption of green m ode is larger than power down mode. in green mode, the program isn?t executed, but the timer with wake - up function actives as enabled, and the timer clock source is the non - stop system clock. the green mode has 2 wake - up sources. one is the p0, p1 level ch ange trigger wake - up. the other one is internal timer with wake - up function occurring overflow. that ? s mean users can setup one fix period to timer, and the system is waked up until the time out. inserting green mode is controlled by cpum1 bit of oscm regi ster. w h en cpum1=1, the system inserts into green mode. after system wake - up from green mode, the cpum1 bit is disabled (zero status) automatically. ? the program stops executing, and full functions are disabled. ? only the timer with wake - up function activ es. ? the oscillator to be the system clock source keeps running, and the other oscillators operation is depend on system operation mode configuration. ? if inserting green mode from normal mode, the system insets to normal mode after wake - up. ? if inserting green mode from slow mode, the system insets to slow mode after wake - up. ? the green mode wake - up sources are p0, p1 level change trigger and unique time overflow. ? pwm output functions active in green mode , but the timer can ? t wake - up the system as overflo w. ? note: sonix provides greenmode macro to control green mode operation. it is necessary to use greenmode macro to control system inserting green mode. the macro includes three instructions. please take care the macro length as using branch type in structions , e.g. bts0, bts1, b0bts0, b0bts1, ins, incms, decs, decms, cmprs, jmp, or the routine would be error.
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 55 version 1. 6 5.6 operating mode contr ol macro sonix provides operating mode control macros to switch system operating mode easily. macro length descript ion sleepmode 1 - word the system insets into sleep mode (power down mode). greenmode 3 - word the system inserts into green mode. slowmode 2 - word the system inserts into slow mode and stops high speed oscillator. slow2normal 5 - word the system returns t o normal mode from slow mode. the macro includes operating mode switch, enable high speed oscillator, high speed oscillator warm - up delay time. ? example: switch normal/slow mode to power down (sleep) mode. sleepmode ; declare ? example: switch normal mode to slow mode. slowmode ; declare ? example: switch slow mode to normal mode (t he external high - speed oscillator stops ). slow2normal ; declare slow2normal macro directly. ? examp le: switch normal/slow mode to green mode. greenmode ; declare ? example: switch normal/slow mode to green mode and enable t0 wake - up function . ; set t0 timer wakeup function . b0bclr ft0ien ; to disable t0 interrupt servi ce b0bclr ft0enb ; to disable t0 timer mov a,#20h ; b0mov t0m,a ; to set t0 clock = fcpu / 64 mov a,#74h b0mov t0c,a ; to set t0c initial value = 74h (to set t0 interval = 10 ms) b0bclr ft0ien ; to disable t0 interrupt service b0bclr ft0irq ; to clear t0 interrupt request b0bset ft0enb ; to enable t0 timer ; go into green mode greenmode ; declare
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 56 version 1. 6 5.7 wakeup 5.7.1 overview under power down mode (sleep mode) or green mode , program doesn ? t execute. the wak eup trigger can wake the system up to normal mode or slow mode. the wakeup trigger sources are external trigger (p0/p1 level change) and internal trigger (t0 timer overflow). the wakeup function builds in interrupt operation issued irq flag and trigger sys tem executing interrupt service routine as system wakeup occurrence . ? power down mode is waked up to normal mode. the wakeup trigger is only external trigger (p0/p1 level change) ? green mode is waked up to last mode (normal mode or slow mode). the wakeup t riggers are external trigger (p0/p1 level change) and internal trigger (t0 timer overflow). ? wakeup interrupt function issues wakeirq as system wakeup from power down mode or green mode. if wakeien is 1 meaning enable, the wakeup event triggers program c ounter point to interrupt vector (org 8) executing interrupt service routine. ? note: if wake - up source is external interrupt source, the wake bit wont be set, and external interrupt irq bit is set. the system issues external interrupt request and execut es interrupt service routine. 5.7.2 wakeup time when the system is in power down mode (sleep mode), the high clock oscillator stops. when waked up from power down mode, mcu waits for 2048 external high - speed oscillator clocks and 32 internal high - speed oscil lator clocks as the wakeup time to stable the oscillator circuit. after the wakeup time, the system goes into the normal mode. ? note : wakeup from green mode is no wakeup time because the clock doesnt stop in green mode. the value of the external high clock oscillator wakeup time is as the following. the wakeup time = 1/fosc * 2048 (sec) + high clock start - up time ? example: in power down mode (sleep mode), the system is waked up. after the wakeup time, the system goes into normal mode. the wakeup ti me is as the following. the wakeup time = 1/fosc * 2048 = 0.512 ms (fosc = 4 mhz ) the total wakeup time = 0.512 ms + oscillator start - up time the value of the internal high clock oscillator rc type wakeup time is as the following. the wakeup time = 1/ fosc * 32 (sec) + high clock start - up time ? example: in power down mode (sleep mode), the system is waked up. after the wakeup time, the system goes into normal mode. the wakeup time is as the following. the wakeup time = 1/fosc * 32 = 2 u s (fhosc = 16 mh z ) ? note : the high clock start - up time is depended on the vdd and oscillator type of high clock.
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 57 version 1. 6 5.7.3 p1w wakeup control register under power down mode (sleep mode) and green mode , the i/o ports with wakeup function are able to wake the system up to no rmal mode. the wake - up trigger edge is level changing. when wake - up pin occurs rising edge or falling edge, the system is waked up by the trigger edge. the port 0 and port 1 have wakeup function. port 0 wakeup function always enables, but the port 1 is con trolled by the p1w register. 0 c0 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1w - p16w p15w p14w p13w p12w p11w p10w read/write - w w w w w w w after reset - 0 0 0 0 0 0 0 bit[6:0] p10w~p1 6 w: port 1 wakeup function control bits. 0 = disable p 1n wakeup function. 1 = enable p1n wakeup function.
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 58 version 1. 6 6 6 6 interrupt 6.1 overview th is mcu provides 7 interrupt sources, including 6 internal interrupt ( t0/ tc 0/cm0/cm1/cm2/adc ) and 1 external interrupt (int0). the external interrupt can wakeup the chip while the system is switched from power down mode to high - speed normal mode , and interrupt request is latched until return to normal mode . once interrupt service is executed, the gie bit in stkp register will clear to 0 for stopping other interrupt request. on the contrast, when interrupt service exits, the gie bit will set to 1 to accept the next interrupts? request. most of the interrupt request signals are stored in intrq register . ? note : the gie bit must enable during all int errupt operation . i n t e n i n t e r r u p t e n a b l e r e g i s t e r i n t e r r u p t e n a b l e g a t i n g i n t r q 7 - b i t l a t c h s p 0 0 i r q i n t e r r u p t v e c t o r a d d r e s s ( 0 0 0 8 h ) g l o b a l i n t e r r u p t r e q u e s t s i g n a l i n t 0 t r i g g e r t 0 t i m e o u t t c 0 t i m e o u t a d c c o n v e r t i n g e n d t 0 i r q c o m p a r a t o r 0 t r i g g e r c o m p a r a t o r 1 t r i g g e r c o m p a r a t o r 2 t r i g g e r t c 0 i r q a d c i r q c m 0 i r q c m 1 i r q c m 2 i r q
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 59 version 1. 6 6.2 inten interrupt enab le register inten is the interrupt request control register including four internal interrupts, three external interrupts enable control bits. one of the register to be set 1 is to enable the interrupt request function. once of the interrupt occur, the stack is incremented and program jump to org 8 to execute interrupt service routines. the program exits the interrupt service routine when the returning interrupt service routine instruction (reti) is executed. 0 c9 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 inten adcien - tc0ien t0ien cm2i en cm1i en cm0i en p00ien read/write r/w - r/w r/w r/w r/w r/w r/w after reset 0 - 0 0 0 0 0 0 bit 0 p00ien: external p0.0 interrupt (int0) control bit. 0 = d isable in t0 interrupt function . 1 = en able int0 interrupt function . bit 1 cm0 ien: comparator 0 interrupt control bit. 0 = d isable comparator 0 interrupt function . 1 = en able comparator 0 interrupt function . bit 2 cm1 ien: comparator 1 interrupt control bit. 0 = d isable comparator 1 interrupt function . 1 = en able comparator 1 interrupt function . bit 3 cm2 ien: comparator 2 interrupt control bit. 0 = d isable comparator 2 interrupt function . 1 = en able comparator 2 interrupt function . bit 4 t0 ien: t0 timer interr upt control bit. 0 = d isable t0 interrupt function . 1 = en able t0 interrupt function . bit 5 t c 0ien: tc0 t imer interrupt control bit. 0 = d isable tc0 interrupt function . 1 = en able tc0 interrupt function . bit 7 adc ien: adc interrupt control bit. 0 = d is able adc interrupt function . 1 = en able adc interrupt function .
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 60 version 1. 6 6.3 intrq interrupt requ est register intrq is the interrupt request flag register. the register includes all interrupt request indication flags. each one of the interrupt request s occurs, the b it of the intrq register would be set 1. the intrq value needs to be clear by programming after detecting the flag. in the interrupt vector of program, users know the any interrupt requests occurring by the register and do the routine corresponding of th e interrupt request. 0 c8 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 intrq adcirq - tc0irq t0irq cm2irq cm1 irq cm0 irq p00irq read/write r/w - r/w r/w r/w r/w r/w r/w after reset 0 - 0 0 0 0 0 0 bit 0 p00i rq : external p0.0 interrupt (int0) requ est flag . 0 = non e int0 interrupt request . 1 = int0 interrupt request . bit 1 cm0 i rq : comparator 0 interrupt request flag . 0 = non e comparator 0 interrupt request . 1 = comparator 0 interrupt request . bit 2 cm1 i rq : comparator 1 interrupt request flag . 0 = non e comparator 1 interrupt request . 1 = comparator 1 interrupt request . bit 3 cm2 i rq : comparator 2 interrupt request flag . 0 = non e comparator 2 interrupt request . 1 = comparator 2 interrupt request . bit 4 t0 i rq : t0 timer interrupt request flag . 0 = non e t0 interrupt request . 1 = t0 interrupt request . bit 5 t c 0i rq : tc0 t imer interrupt request flag. 0 = non e tc0 interrupt request . 1 = tc0 interrupt request . bit 7 adc i rq : adc interrupt request flag. 0 = non e adc interrupt request . 1 = adc interrupt request .
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 61 version 1. 6 6.4 gie global interrupt operation gie is the global interrupt control bit. all interrupts start work after the gie = 1 it is necessary for interrupt service request. one of the interrupt requests occurs, and the program counter (pc) points to th e interrupt vector (org 8) and the stack add 1 level. 0dfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stkp gie - - - - stkpb2 stkpb1 stkpb0 read/write r/w - - - - r/w r/w r/w after reset 0 - - - - 1 1 1 bit 7 gie: global interrupt control bit . 0 = disable global interrupt. 1 = enable global interrupt. ? example: set global interrupt control bit (gie). b0bset fgie ; enable gie ? note : the gie bit must enable during all interrupt operation .
sn8p2740 series adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 62 version 1. 6 6.5 push, pop routine when any interrupt occur s, system will jump to org 8 and execute interrupt service routine. it is necessary to save acc, pflag data. the chip includes push , pop for in/out interrupt service routine. the two instructions save and load acc , pflag data into buffers and avoid mai n routine error after interrupt service routine finishing. ? note : push , pop instructions save and load acc/pflag without ( nt0, npd). push/pop buffer is an unique buffer and only one level . ? example: store acc and paflg data by push, pop instructi ons when interrupt service routine executed. org 0 jmp start org 8 jmp int_service org 10h start: push ; save acc and pflag to buffers. pop ; l oad acc and pflag from buffers. reti ; exit interrupt service vector
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 63 version 1. 6 6.6 external interrupt o peration (int0) sonix provides 1 external interrupt source s in the micro - controller. int0 is external interrupt trigger sources and build in edge trigger configuration function. when the external edge trigger occurs, the external interrupt request flag will be set to 1 when the external interrupt control bit enabled. if the external interrupt control bit is disabled, the external interrupt request flag won ? t active wh en external edge trigger occurrence. when external interrupt control bit is enabled and external interrupt edge trigger is occurring, the program counter will jump to the interrupt vector (org 8) and execute interrupt service routine. the external interru pt builds in wake - up latch function. that means when the system is triggered wake - up from power down mode , the wake - up source is external interrupt source (p0.0), and the trigger edge direction matches interrupt edge configuration, the trigger edge will be latched, and the system executes interrupt service routine fist after wake - up. 0 b fh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pedge - - - - - - p00g1 p00g0 read/write - - - - - - r/w r/w after reset - - - - - - 0 0 bit[ 1 : 0 ] p0 0 g[1:0]: int0 ed ge trigger select bits. 00 = reserved, 01 = ris ing edge, 10 = falling edge, 11 = rising/falling bi - direction. ? example: setup int0 interrupt request and bi - direction edge trigger. mov a, #03h b0mov pedge, a ; set int0 interrupt trigger as bi - direction edge. b0bset fp00ien ; e nable int0 interrupt service b0bclr f p00 irq ; c lear int0 interrupt request flag b0bset fgie ; enable gie ? example: int0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ; pu sh routine to save acc and pflag to buffers. b0bts1 fp00irq ; check p00irq jmp exit_int ; p00irq = 0, exit interrupt vector b0bclr fp00irq ; reset p00irq exit_int: ; pop routine to load acc and pflag from buffers. reti ; exit interrupt vector
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 64 version 1. 6 6.7 t0 interrupt operati on when the t0c counter occurs overflow, the t0irq will be set to 1 however the t0ien is enable or disable. if the t0ien = 1, the trigger event will make the t0irq to be 1 and the system enter interrupt vector. if the t0ien = 0, the trigger event will make the t0irq to be 1 but the system will not enter interrupt vector. users need to care for the operation under multi - interrupt situation. ? example: t0 interrupt request setup . fcpu = 4mhz / 4. b0bclr ft 0 ien ; d isable t 0 interrupt service b0bclr ft 0 enb ; d isable t 0 timer mov a, #20h ; b0mov t 0 m, a ; s et t 0 clock = f cpu / 64 mov a, # 6 4h ; s et t 0 c initial value = 6 4h b0mov t 0 c, a ; s et t 0 interval = 10 ms b0bs et ft 0 ien ; e nable t 0 interrupt service b0bclr ft 0 irq ; c lear t 0 interrupt request flag b0bset ft 0 enb ; e nable t 0 timer b0bset fgie ; enable gie ? example: t0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_servi ce: b0bts1 ft0irq ; check t0irq jmp exit_int ; t0irq = 0, exit interrupt vector b0bclr ft0irq ; reset t0irq mov a, #64h b0mov t0c, a ; reset t0c. ; t0 interrupt service routine
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 65 version 1. 6 6.8 tc0 interrupt operat ion when the tc0c counter overflows, the tc0irq will be set to 1 no matter the tc0ien is enable or dis able. if the tc0ien and the trigger event tc0irq is set to be 1. as the result, the system will execute the interrupt vector. if the tc0ien = 0, the trigger event tc0irq is still set to be 1. moreover, the system won?t execute interrupt vector even w hen the tc0ien is set to be 1. users need to be cautious with the operation under multi - interrupt situation. ? example: tc0 interrupt request setup. fcpu = 16mhz / 16. b0bclr ftc0ien ; disable tc0 interrupt service b0bclr ftc0enb ; disable tc0 timer mov a, #20h ; b0mov tc0m, a ; set tc0 clock = fcpu / 64 mov a, # 6 4h ; set tc0c initial value = 6 4h b0mov tc0c, a ; set tc0 interval = 10 ms b0bset ftc0ien ; enable tc0 interrupt service b0bclr ftc0irq ; clear tc0 interrupt request flag b 0bset ftc0enb ; enable tc0 timer b0bset fgie ; enable gie ? example: tc0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0bts1 ftc0irq ; check tc0irq jmp exit_int ; tc0irq = 0, exit interrupt vector b0bclr ftc0irq ; reset tc0irq mov a, # 6 4h b0mov tc0c, a ; reset tc0c. ; tc0 interrupt service routine
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 66 version 1. 6 6.9 adc interrupt operat ion when the adc converting successfully, the adcirq will be set to 1 no matter the adcien is enable or disable. if the adcien and the trigger event adcirq is set to be 1 . as the result, the system will execute the interrupt vector. if the adcien = 0, the trigger event adcirq is still set to be 1 . moreover, the system won ? t execute interrupt vector even when the adcien is set to be 1 . users need to be cautious with the operation under multi - interrupt situation. ? example: adc interrupt request setup. b0bclr f adc ien ; d isable adc interrupt service mov a, # 10110000b ; b0mov adm , a ; enable p4.0 adc input and adc function. mov a, # 00000000b ; s et adc converting rate = fcpu/16 b0mov adr , a b0bset f adc ien ; e nable adc interrupt service b0bclr f adc irq ; c lear adc interrupt request flag b0bset fgie ; enable gie b0bset f ads ; start adc transformation ? example: adc interrupt service routine. org 8 ; int errupt vector jmp int_service int_service: b0bts1 fadcirq ; check adcirq jmp exit_int ; adcirq = 0, exit interrupt vector b0bclr fadcirq ; reset adcirq ; adc interrupt service routine
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 67 version 1. 6 6.10 comparator interrupt operation (cmp0~cmp2 ) sonix provides 3 sets comparator with interrupt function in the micro - controller . the comparator interrupt trigger edge direction is controlled by comparator register. cm0g of cm0m is control comparator 0 interrupt trigger edge direction. cm1g of cm1m is control comparator 1 interrupt trigger edge direction. cm2g of cm2m is control co mparator 2 interrupt trigger edge direction. when the comparator output status transition occurs, the comparator interrupt request flag will be set to 1 no matter the comparator interrupt control bit status. the comparator interrupt flag doesn? t active o nly when comparator control bit is disabled. when comparator interrupt control bit is enabled and comparator interrupt edge trigger is occurring, the program counter will jump to the interrupt vector (org 8) and execute interrupt service routine. 09ch bi t 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cm0m cm0en cm0oen cm0out cm0 sf cm0g - - - read/write r/w r/w r/w r/w r/w - - - after reset 0 0 0 0 0 - - - bit 3 cm0g: comparator 0 interrupt trigger direction control bit. 0 = falling edge trigger. c ompar ator output status is from high to low as cm0p < cm0n . 1 = rising edge trigger. c omparator output status is from low to high as cm0p > cm0n . 09dh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cm1m cm 1 en cm 1 oen cm 1 out cm 1sf cm 1 g cm1rs2 cm1rs1 cm1rs0 re ad/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 3 cm1g: comparator 1 output trigger direction control bit. 0 = falling edge trigger. comparator output status is from high to low as cm1p < cm1n. 1 = rising edge trigger. comparato r output status is from low to high as cm1p > cm1n. 09eh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cm2m cm2en cm2oen cm2out cm2 sf cm2g cm2rs2 cm2rs1 cm2rs0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 3 cm 2 g: compa rator 2 output trigger direction control bit. 0 = falling edge trigger. comparator output status is from high to low as cm 2 p < cm 2 n. 1 = rising edge trigger. comparator output status is from low to high as cm 2 p > cm 2 n. ? example: setup comparator 0 interrup t request and falling edge trigger. mov a, #00h b0mov cm0m, a ; set comparator 0 interrupt trigger as bi - direction edge. b0bset f cm0 ien ; e nable comparator 0 interrupt service b0bclr f cm0 irq ; c lear comparator 0 interrupt request flag b0bset f cm0 en ; e nable comparator 0. b0bset fgie ; enable gie ? example: comparator 0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ; push routine to save acc and pflag to buffers. b0bts1 fcm0irq ; chec k cm0irq jmp exit_int ; cm0irq = 0, exit interrupt vector b0bclr fcm0irq ; reset cm0irq exit_int: ; pop routine to load acc and pflag from buffers. reti ; exit interrupt vector
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 68 version 1. 6 6.11 multi - in terrupt operation under certain condition, the software designer uses more than one interrupt requests. processing multi - interrupt request requires setting the priority of the interrupt requests. the irq flags of interrupts are controlled by the interrupt event. nevertheless, the irq flag 1 doesn ? t mean the system will execute the interrupt vector. in addition, which means the irq flags can be set 1 by the events without enable the interrupt. once the event occurs, the irq will be logic 1 . the irq an d its trigger event relationship is as the below table. interrupt name trigger event description p00irq p0.0 trigger controlled by pedge t0irq t0c overflow tc0irq tc0c overflow adcirq adc converting end. cm0irq comparator 0 output level transition. cm1irq comparator 1 output level transition. cm2irq comparator 2 output level transition. for multi - interrupt conditions, two things need to be taking care of . one is to set the priority for these interrupt requests. two is using ien and irq flags to decide which interrupt to be executed. users have to check interrupt control bit and interrupt request flag in interrupt routine. ? example: check the interrupt request under multi - interrupt operation org 8 ; interrupt vector jmp int_service int_ser vice: intp00chk: ; check int0 interrupt request b0bts1 fp00ien ; check p00ien jmp intt0chk ; jump check to next interrupt b0bts0 fp00irq ; check p00irq jmp intp00 intt0chk: ; check t0 interrupt request b0bts1 ft0ien ; check t0ien jmp inttc0chk ; jump check to next interrupt b0bts0 ft0irq ; check t0irq jmp intt0 ; j ump to t0 interrupt service routine inttc0chk: ; check tc0 interrupt request b0bts1 ftc0ien ; check t c0ien jmp intadchk ; jump check to next interrupt b0bts0 ftc0irq ; check tc0irq jmp inttc0 ; j ump to tc0 interrupt service routine intadchk: ; check adc interrupt request b0bts1 fadcien ; check adcien jmp
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 69 version 1. 6 7 7 7 i/o port 7.1 overview the micro - controller builds in 22 p in i/o. most of the i/o pins are mixed with analog pins and special function pins. the i/o shared pin list is as following. i/o pin shared pin shared pin control condition name type name type p0.0 i/o int0 dc p00ien=1 p0.1 o pwm 0 dc pw m0out =1 . p0.2 i/o cm 0 p ac cm0en=1 p0.3 i/o cm 0 n ac cm0en=1 p0. 4 i rst dc reset_pin code option = reset vpp hv otp programming p0. 5 i/o xout ac high_clk code option = 32k, 4m, 12m bz dc bzen=1 p0. 6 i/o xin ac high_clk code option = rc, 32k, 4m, 12m p1.0 i/o op n ac open=1 p1.1 i/o opp ac open=1 p1.2 i/o opo ac open=1 p1.3 i/o cm 2 n ac cm2en=1 p1.4 i/o cm 2 p ac cm2en=1, cm2rs[2:0]=000b p1.5 i/o cm1n ac cm1en=1 p1.6 i/o cm1p ac cm1en=1, cm1rs[2:0]=000b p4.0 i/o ain0 ac adenb=1, gchs=1, chs[2: 0 ] = 000b avre fh ac adenb=1, avrefh=1 p4 [7:1] i/o ain [7: 1 ] ac adenb=1, gchs=1, chs[2: 0 ] = 001b~111b * dc: digital characteristic. ac: analog characteristic. hv: high voltage characteristic.
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 70 version 1. 6 7.2 i/o port mode the port direction is programmed by pnm register. when the bit of pnm register is 0 , the pin is input mode. when the bit of pnm register is 1 , the pin is output mode. 0b8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p 0 m - p0 6 m p0 5 m - p0 3 m p02m - p00m read/write - r/w r/w - r/w r/w - r/w after reset - 0 0 - 0 0 - 0 0c1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p 1 m - p16m p15m p14m p13m p12m p11m p10m read/write - r/w r/w r/w r/w r/w r/w r/w after reset - 0 0 0 0 0 0 0 0 c 4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p 4 m p 47 m p 46 m p 45 m p 44 m p 43 m p 4 2m p 41 m p 4 0m read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit[7:0] pnm[7:0]: pn mode control bits. (n = 0~4). 0 = pn is input mode. 1 = pn is output mode. ? note : 1. users can program them by bit control instruct ions (b0bset, b0bclr). 2. p0.4 input pin only, and the p0m.4 is undefined ? example: i/o mode selecting clr p0m ; set all ports to be input mode. clr p4m mov a, #0ffh ; set all ports to be output mode. b0mov p0m, a b0mov p4m,a b0 bclr p4m.0 ; set p4.0 to be input mode. b0bset p4m.0 ; set p4.0 to be output mode.
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 71 version 1. 6 7.3 i/o pull up register the i/o pins build in internal pull - up resistors and only support i/o input mode. the port internal pull - up resistor is programmed by pnur r egister. when the bit of pnur register is 0 , the i/o pin ? s pull - up is disabled. when the bit of pnur register is 1 , the i/o pin ? s pull - up is enabled. 0 e 0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p 0 ur - p0 6 r p0 5 r - p0 3 r p02r - p00r read/writ e - w w - w w - w after reset - 0 0 - 0 0 - 0 0 e 1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p 1 ur - p16r p15r p14r p14r p12r p11r p10r read/write - w w w w w w w after reset - 0 0 0 0 0 0 0 0 e 4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p 4 ur p 47 r p 46 r p 45 r p 44 r p 43 r p 42 r p 41 r p 40 r read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 ? note : p0.4 is input only pin and without pull - up resister. the p0ur.4 is undefined. ? example: i/o pull up register mov a, #0ffh ; enable p or t0, 4 pull - up register, b0mov p 0 ur , a ; b0mov p4ur,a
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 72 version 1. 6 7.4 i/o port data regist er 0 d0 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0 - p0 6 p0 5 p04 p03 p02 p01 p00 read/write - r /w r /w r r /w r/w w r/w after reset - 0 0 0 0 0 0 0 0 d 1h bit 7 bi t 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p 1 - p16 p15 p14 p13 p12 p11 p10 read/write - r/w r/w r/w r/w r/w r/w r/w after reset - 0 0 0 0 0 0 0 0 d 4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p 4 p47 p46 p45 p44 p43 p42 p41 p40 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 ? note : 1. the p04 keeps 1 when external reset enable by code option. 2. if set one bit of p0 register ( p0.n bit ), recommend using mov or b0mov instructions to control the bit, not use read & modify write type instructions (e.g. bset, bclr, b0bset, b0bclr ), or the write only type bit (p0.1) is modified after executing instruction . ? example: read data fro m input port. b0mov a, p0 ; read data from port 0 b0mov a, p4 ; read data from port 4 ? example: write data to output port. mov a, #0ffh ; write data ffh to all port. b0mov p0, a b0mov p4, a ? example: write one bit data to output port. b0bset p4.0 ; set p4.0 to be 1 . b0bclr p4.0 ; set p4.0 to be 0 .
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 73 version 1. 6 7.5 port 4 adc sha re pin the port 4 is shared with adc input function and no schmitt trigger structure. only one pin of port 4 can be configured as adc input in the same time by adm register. the other pins of port 4 are digital i/o pins. connect an analog signal to coms di gital input pin, especially the analog signal level is about 1/2 vdd will cause extra current leakage. in the power down mode, the above leakage current will be a big problem. unfortunate ly, if users connect more than one analog input signal to port 4 will encounter above current leakage situation. p4con is port4 configuration register. write 1 into p4con.n will configure related port 4 pin as pure analog input pin to avoid current leakage. 0aeh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p4con p4c on7 p4con6 p4con5 p4con4 p4con3 p4con2 p4con1 p4con0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit[4:0] p4con[7:0]: p4.n configuration control bits. 0 = p4.n can be an analog input (adc input) or digital i/o pins. 1 = p4.n is pure analog input, can ? t be a digital i/o pin. ? note: when port 4 .n is general i/o port not adc channel, p4con .n must set to 0 or the port 4 .n digital i/o signal would be isolated . port 4 adc analog input is controlled by gchs and chsn bits o f adm register. if gchs = 0, p4.n is general purpose bi - direction i/o port. if gchs = 1, p4.n pointed by chsn is adc analog signal input pin. 0b1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adm adenb ads eoc gchs avrefh chs2 chs1 chs0 read/write r /w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 4 gchs: global channel select bit. 0 = disable ain channel. 1 = enable ain channel. bit 3 avrefh: adc external high reference voltage input pin control bit. 0 = adc high reference voltage is from internal vdd. p4.0 is gpio or ain0 pin. 1 = enable adc external high reference voltage input pin from p4.0. bit[2:0] chs[2:0]: adc input channels select bit. 000 = ain0, 001 = ain1, 010 = ain2, 011 = ain3, 100 = ain4, 101 = ain5, 110 = ain6, 111 = ain7. ? note: for p4.n general purpose i/o function, users should make sure of p4.n s adc channel is disabled, or p4.n is automatically set as adc analog input when gchs = 1 and chs[2:0] point to p4.n.
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 74 version 1. 6 ? example: set p4.1 to be general p urpose input mode. p4con.1 must be set as 0 . ; check gchs and chs[2:0] status. b0bclr fgchs ;if chs[2:0] point to p4.1 (chs[2:0] = 001b), set gchs=0 ;if chs[2:0] dont dont ; clear p4con. b0bclr p4con.1 ; enable p4.1 digital function. ; enable p4.1 input mode. b0bclr p4m.1 ; set p4.1 as input mode. ? example: set p4.1 to be general purpose output. p4con.1 must be set as 0 . ; check gchs and chs[2:0] status. b0bclr fgchs ;if chs[2:0] point to p4.1 (chs[2:0] = 001b), set gchs=0. ;if chs[2:0] dont dont ; clear p4con. b0bclr p4con.1 ; enable p4.1 digital function. ; set p4.1 output buffer to avoid glitch. b0bset p4.1 ; set p4.1 buffer as 1 . ; or b0bclr p4.1 ; set p4.1 buffer as 0 . ; enabl e p4.1 output mode. b0bset p4m.1 ; set p4.1 as input mode. p4.0 is shared with general purpose i/o, adc input (ain0) and adc external high reference voltage input. avrefh flag of adm register is external adc high reference voltage input control bit. if avrefh is enabled, p4.0 general purpose i/o and adc analog input (ain0) functions are disabled. p4.0 pin is connected to adc high reference voltage directly. ? note: for p4.0 general purpose i/o and ain0 functions, avrefh must be set as 0 . ? example: set p4.0 to be general purpose input mode. avrefh and p4con.0 bits must be set as 0 . ; check avrefh status. b0bts0 favrefh ; check avrefh = 0. b0bclr favrefh ; avrefh = 1, clear it to disable external adc high reference input. ; avrefh = 0, exec ute next routine. ; check gchs and chs[2:0] status. b0bclr fgchs ;if chs[2:0] point to p4.0 (chs[2:0] = 000b), set gchs=0 ;if chs[2:0] dont dont ; clear p4con. b0bclr p4con.0 ; enable p4.0 digital function. ; enable p4.0 input mode. b0bclr p4m.0 ; set p4.0 as input mode.
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 75 version 1. 6 ? example: set p4.0 to be general purpose output. evhenb and p4con.0 bits must be set as 0 . ; check avrefh status. b0bts0 favrefh ; check avrefh = 0. b0bclr favrefh ; avrefh = 1, clear it to disable external adc high reference input. ; avrefh = 0, execute next routine. ; check gchs and chs[2:0] status. b0bclr fgchs ;if chs[2:0] point to p4.0 (chs[2:0] = 000b), set gchs=0 ;if chs[2:0] dont dont ; clear p4con. b0bclr p4con.0 ; enable p4.0 digital function. ; set p4.0 output buffer to avoid glitch. b0bset p4.0 ; set p4.0 buffer as 1 . ; or b0bclr p4.0 ; set p4.0 buffer as 0 . ; enabl e p4.0 output mode. b0bset p4m.0 ; set p4.0 as input mode.
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 76 version 1. 6 8 8 8 timer s 8.1 watchdog timer the watchdog timer (wdt) is a binary up counter designed for monitoring program execution. if the program g oe s into the unknown status by noise interference, wdt overf low signal raises and resets mcu. watchdog clock controlled by code option and the clock source is internal low - speed oscillator. watchdog overflow time = 8192 / internal low - speed oscillator (sec). vdd internal low rc freq. watchdog overflow time 3v 16khz 512ms 5v 32khz 256ms the watchdog timer has three operating options controlled watchdog code option. ? disable: disable watchdog timer function. ? enable: enable watchdog timer function. watchdog timer actives in normal mode and slow mode. in pow er down mode and green mode, the watchdog timer stops. ? always_on: enable watchdog timer function. the watchdog timer actives and not stop in power down mode and green mode. in high noisy environment, the always_on option of watchdog operations is the strongly recommend ation to make the system reset under error situations and re - start again. watchdog clear is controlled by wdtr register. moving 0x5a data into wdtr is to reset watchdog timer. 0cch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wdtr wdtr7 wdtr6 wdtr5 wdtr4 wdtr3 wdtr2 wdtr1 wdtr0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 ? example : an operation of watchdog timer is as following. to clear the watchdog timer counter in the top of the main routine of the program. main: mov a, #5ah ; clear the watchdog timer . b0mov wdtr, a ? example : clear watchdog timer by @rst_wdt macro of sonix ide. main: @rst_wdt ; clear the watchdog timer .
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 77 version 1. 6 watchdog timer application note is as following. ? before clearing watchdog timer, check i/o status and check ram contents can improve system error. ? don?t clear watchdog timer in interrupt vector and interrupt service routine. that can improve main routine fail. ? clearing watchdog timer program is only at one part of the program. this way is the best structure to enhance the watchdog timer function. ? example : an operation of watchdog timer is as following. to clear the watchdog timer counter in the top of the main routine of the program. main: don?t mov a, #5ah ; clear the watchdog timer . b0mov wdtr, a call sub1 call sub2
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 78 version 1. 6 8.2 t0 8 - bit basic timer 8.2.1 overview the t0 timer is an 8 - bit binary u p timer with basic timer function. the basic timer function supports flag indicator (t0irq bit) and interrupt operation (interrupt vector). the interval time is programmable through t0m, t0c registers. the t0 builds in green mode wake - up function. when t0 timer overflow occurs under green mode, the system will be waked - up to last operating mode. ? 8 - bit programmable up counting timer: generate time - out at specific time intervals based on the selected clock frequency. ? interrupt function: t 0 timer function su pport s interrupt function. when t 0 timer occurs overflow, the t 0 irq actives and the system points program counter to interrupt vector to do interrupt sequence. ? green mode function: t0 timer keep s running in green mode and wake s up system when t0 timer ove rflows . 8.2.2 t0 timer operation t0 timer is controlled by t0 enb bit. when t0 enb= 0 , t0 timer stops. when t0enb=1, t0 timer starts to count. t0c increases 1 by timer clock source. when t0 overflow event occurs, t0irq flag is set as 1 to indicate overflow and cleared by program. the overflow condition is t0c count from full scale (0xff) to zero scale (0x00). t0 doesn ? t build in double buffer, so load t0c by program when t0 timer overflows to fix the correct interval time. if t0 t imer interrupt function is enabled (t0ien=1), the system will execute interrupt procedure. the interrupt procedure is system program counter points to interrupt vector (org 8) and executes interrupt service routine after t0 overflow occurrence. clear t0irq by program is necessary in interrupt procedure. t0 timer can works in normal mode, slow mode and green mode. in green mode, t0 keeps counting, set t0irq and wakes up system when t0 timer overflows. f c p u t 0 r a t e ( f c p u / 2 ~ f c p u / 2 5 6 ) t 0 e n b c p u m 0 , 1 t 0 c 8 - b i t b i n a r y u p c o u n t i n g c o u n t e r t 0 i r q i n t e r r u p t f l a g ( t 0 t i m e r o v e r f l o w . ) l o a d t 0 c v a l u e b y p r o g r a m . 0 x 0 0 o r n b y p r o g r a m . . . . . . c l o c k s o u r c e t 0 c t 0 i r q t 0 t i m e r o v e r f l o w s . t 0 i r q s e t a s 1 . r e l o a d t 0 c b y p r o g r a m . t 0 i r q i s c l e a r e d b y p r o g r a m . 0 x 0 1 o r n + 1 0 x f e 0 x f f . . . . . . 0 x 0 0 o r n b y p r o g r a m 0 x 0 2 o r n + 2 0 x 0 2 o r n + 2
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 79 version 1. 6 t0 clock source is fcpu (instruction cycle) through t0 rate[2:0] pre - scaler to decide fcpu/2~fcpu/256. t0 length is 8 - bit (256 steps), and the one count period is each cycle of input clock. t0rate[2:0] t0 clock t0 interval time fhosc=16mhz, fcpu=fhosc/4 fhosc=16mhz, fcpu=fh osc/16 max. (ms) unit (us) max. (ms) unit (us) 000b fcpu/256 16.384 64 65.536 256 001b fcpu/128 8.192 32 32.768 128 010b fcpu/64 4.096 16 16.384 64 011b fcpu/32 2.048 8 8.192 32 100b fcpu/16 1.024 4 4.096 16 101b fcpu/8 0.512 2 2.048 8 110b fcpu/ 4 0.256 1 1.024 4 111b fcpu/2 0.128 0.5 0.512 2 8.2.3 t0m mode register t0 m is t0 timer mode control register to configure t0 operating mode including t0 pre - scaler, clock source these configurations must be setup completely before enabling t0 timer. 0 d 8h b it 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0 m t0 enb t0 rate2 t0 rate1 t0 rate0 - - - - read/write r/w r/w r/w r/w - - - - after reset 0 0 0 0 - - - - bit [6:4] t0 rate[2:0]: t0 timer clock source select bits. 000 = fcpu/ 256 , 001 = fcpu/ 128 , 010 = fc pu/ 64 , 011 = fcpu/ 32 , 100 = fcpu/ 16 , 101 = fcpu/ 8 , 110 = fcpu/ 4 , 111 = fcpu/ 2 . bit 7 t0enb: t0 counter control bit. 0 = d isable t0 timer. 1 = enable t0 timer . 8.2.4 t0c counting register t0c is t0 8 - bit counter. when t0c overflow occurs, the t0irq flag is s et as 1 and cleared by program. the t0c decides t0 interval time through below equation to calculate a correct value. it is necessary to write the correct value to t0c register, and then enable t0 timer to make sure the fist cycle correct. after one t0 o verflow occurs, the t0c register is loaded a correct value by program. 0 d 9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0c t0c7 t0c6 t0c5 t0c4 t0c3 t0c2 t0c1 t0c0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 the equati on of t0c initial value is as following. t0c initial value = 256 - (t0 interrupt interval time * t0 clock rate ) ? example: to calculation t0c to obtain 10ms t0 interval time. t0 clock source is fcpu = 16mhz/16 = 1mhz. select t0rate=001 (fcpu/128). t0 interval time = 10ms. t0 clock rate = 16 mhz/ 16 /128 t0 c initial value = 256 - (t0 interval time * input clock) = 256 - (10ms * 16mhz / 16 / 128 ) = 256 - ( 10 - 2 * 16mhz / 16 / 128 ) = b2h
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 80 version 1. 6 8.2.5 t0 timer operation explame ? t0 timer configuration : ; reset t0 timer . clr t0m ; clear t0 m register. ; set t0 clock source and t0 rate. mov a, #0 nnn 0 0 00b b0mov t0 m, a ; set t0 c register for t0 interval time. mov a, # value b0mov t0 c, a ; clear t0 irq b0bclr f t0 irq ; enable t0 time r and interrupt function. b0bset ft0ien ; enable t0 interrupt function. b0bset ft0enb ; enable t0 timer.
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 81 version 1. 6 8.3 tc0 8 - bit timer/counter 8.3.1 overview the tc0 timer is an 8 - bit binary up timer with basic timer, pwm function and pulse generator. the basic timer function supports flag indicator (tc0irq bit) and interrupt operation (interrupt vector). the interval time is programmable through tc0m, tc0c, tc0r registers. tc0 builds in duty/cycle programmable pwm. the pwm cycle and resolution are controlled by tc0 t imer clock rate, tc0r and tc0d registers, so the pwm with good flexibility to implement ir carry signal, motor control and brightness adjuster tc0 timer also builds in pulse generator function. the pulse generator function is one cycle pwm format as start trigger occurrence. the pulse output trigger source has tc0po control bit and comparator 0 output edge controlled by register. tc0 counter supports auto - reload function which always enabled. when tc0 timer overflow occurs, the tc0c will be reloaded from tc 0r automatically. the auto - reload function is always enabled. the tc0 doesn?t build in green mode wake - up function. the main purposes of the tc0 timer are as following. ? 8 - bit programmable up counting timer: generate time - out at specific time intervals bas ed on the selected clock frequency. ? interrupt function: tc0 timer function supports interrupt function. when tc0 timer occurs overflow, the tc0irq actives and the system points program counter to interrupt vector to do interrupt sequence. ? duty/cycle prog rammable pwm: the pwm is duty/cycle programmable controlled by tc0r and tc0d registers. ? pulse generator: the pulse generator function is one cycle pwm format as start trigger occurrence. the pulse output trigger source has tc0po control bit and comparator 0 output edge controlled by register. when tc0po = 1, cm0sf = 0, the pulse generator trigger is pwm0out bit. when tc0po = 1, cm0sf = 1, the pulse generator trigger is comparator 0 output edge. ? green mode function: all tc0 functions (timer, pwm, pulse gen erator ) keeps running in green mode, but no wake - up function. timer irq actives as any irq trigger occurrence, e.g. timer overflow 2 4 8 1 6 3 2 6 4 1 2 8 2 5 6 t c 0 r a t e c o m p a r a t o r 0 o u t p u t t c 0 e n b c p u m 0 , 1 t c 0 c 8 - b i t b i n a r y u p c o u n t i n g c o u n t e r t c 0 r r e l o a d d a t a b u f f e r s r t c 0 t i m e o u t t c 0 i r q p 0 . 1 o u t p u t p 0 . 1 p i n p w m p w m 0 o u t = 1 , t c 0 p o = 0 l o a d c o m p a r e t c 0 d d a t a b u f f e r u p c o u n t i n g r e l o a d v a l u e f c p u f h o s c t c 0 c k s c o m p a r e t c 0 t i m e o u t p w m 0 o u t = 0 , t c 0 p o = 0 t c 0 p o = 1 t c 0 p o p w m 0 o u t c m 0 s f t c 0 d i r p u l s e g e n e r a t o r
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 82 version 1. 6 8.3.2 tc0 timer operation tc0 timer is controlled by tc0enb bit. when tc0enb= 0 , tc0 timer stops. when tc0enb=1, tc0 timer starts to count. before enabling tc0 timer, setup tc0 timer ? s configurations to select timer function modes, e.g. basic timer, interrupt function tc0c increases 1 by timer clock source. when tc0 overflow event occurs, tc0irq fla g is set as 1 to indicate overflow and cleared by program. the overflow condition is tc0c count from full scale (0xff) to zero scale (0x00). in difference function modes, tc0c value relates to operation. if tc0c value changing effects operation, the tran sition of operations would make timer function error. so tc0 builds in double buffer to avoid these situations happen. the double buffer concept is to flash tc0c during tc0 counting, to set the new value to tc0r (reload buffer), and the new value will be l oaded from tc0r to tc0c after tc0 overflow occurrence automatically. in the next cycle, the tc0 timer runs under new conditions, and no any transitions occur. the auto - reload function is no any control interface and always actives as tc0 enables. if tc0 ti mer interrupt function is enabled (tc0ien=1), the system will execute interrupt procedure. the interrupt procedure is system program counter points to interrupt vector (org 000ch) and executes interrupt service routine after tc0 overflow occurrence. clear tc0irq by program is necessary in interrupt procedure. tc0 timer can works in normal mode, slow mode and green mode. but in green mode, tc0 keep counting, set tc0irq and outputs pwm, but can ? t wake - up system. tc0 provides diff erent clock sources to implement different applications and configurations. tc0 clock source includes fcpu (instruction cycle) and fhosc (high speed oscillator) controlled by tc0cks bit . tc0cks bit selects the clock source is from fcpu or fhosc. if tc0cks= 0, tc0 clock source is fcpu through tc0rate[2:0] pre - scal a r to decide fcpu/2~fcpu/256. if tc0cks=1, tc0 clock source is fhosc through tc0rate[2:0] pre - scal a r to decide fhosc/2~fhosc/256 . tc0 length is 8 - bit (256 steps), and the one count period is each cyc le of input clock. tc0cks tc0rate[2:0] tc0 clock tc0 interval time fhosc=16mhz, fcpu=fhosc/ 4 fhosc=4mhz, fcpu=fhosc/4 max. (ms) unit (us) max. (ms) unit (us) 0 000b fcpu/ 256 16.384 64 65.536 256 0 001b fcpu/ 128 8.192 32 32.768 128 0 010b fcp u/ 64 4.096 16 16.384 64 0 011b fcpu/ 32 2.048 8 8.192 32 0 100b fcpu/ 16 1.024 4 4.096 1 6 0 101b fcpu/ 8 0.512 2 2.048 8 0 110b fcpu/ 4 0.256 1 1.024 4 0 111b fcpu/ 2 0.128 0.5 0.512 2 1 000b fhosc /256 4.096 16 16.384 64 1 001b fhosc /128 2.048 8 8.192 32 1 010b fhosc /64 1.024 4 4.096 16 1 011b fhosc /32 0.512 2 2.048 8 1 100b fhosc /16 0.256 1 1.024 4 1 101b fhosc /8 0.128 0.5 0.512 2 1 110b fhosc /4 0.064 0.25 0.256 1 1 111b fhosc /2 0.032 0.125 0.128 0.5 0 x 0 0 o r t c 0 r . . . . . . c l o c k s o u r c e t c 0 c t c 0 i r q t c 0 t i m e r o v e r f l o w s . t c 0 i r q s e t a s 1 . r e l o a d t c 0 c f r o m t c 0 r a u t o m a t i c a l l y . t c 0 i r q i s c l e a r e d b y p r o g r a m . 0 x 0 1 0 x 0 2 0 x 0 3 0 x f e 0 x f f t c 0 r . . . . . .
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 83 version 1. 6 8.3.3 pulse width modulation (pwm) tc0 timer build s in pwm function controlled by pwm0out bit. pwm output pin is shared with gpio. when pwm0out=1, the pwm function is enabled and gpio pin is switched from gpio to pwm output status. when pwm0out=0, pwm output pin returns to gpio last status. pwm signal is generated from the result of tc0c, tc0r and tc0d comparison. when pwm0out=1 or tc0c counts from 0xff to 0x00 (overflow), the pwm outputs high status which is the pwm initial status. tc0c is loaded new data from tc0r register to decide pwm cycle and resolut ion. tc0c keeps counting, and the system compares tc0c and tc0d. when tc0c=tc0d, the pwm output status exchanges to low. tc0c keeps counting. when tc0 timer overflow occurs, and one cycle of pwm signal finishes. tc0c is reloaded from tc0r automatically, an d pwm output status exchanges to high for next cycle. tc0d decides the high duty duration, and tc0r decides the resolution and cycle of pwm. tc0r can?t be larger than tc0d, or the pwm signal is error. the pwm output phase can be selected through tc0dir bit . when tc0dir = 0, pwm?s phase is high pulse and low idle status. when tc0dir = 1, pwm?s phase is low pulse and high idle status. the resolution of pwm is decided by tc0r. tc0r range is from 0x00~0xff. if tc0r = 0x00, pwm ? s resolution is 1/256. if tc0r = 0x80, pwm ? s resolution is 1/128. tc0d controls the high pulse width of pwm for pwm ? s duty. when tc0c = tc0d, pwm output exchanges to low status. tc0d must be greater than tc0r, or the pwm signal keeps low status. when pwm out puts, tc0irq still actives as tc0 overflows, and tc0 interrupt function actives as tc0ien = 1. but strongly recommend be careful to use pwm and tc0 timer together, and make sure both functions work well. the pwm output pin is shared with gpio and switch t o output pwm signal as pwm0out=1 automatically. if pwm0out bit is cleared to disable pwm, the output pin exchanges to last gpio mode automatically. it easily to implement carry signal on/off operation, not to control tc0enb bit. t c 0 r t c 0 r + 1 t c 0 r + 2 t c 0 c . . . t c 0 d - 2 t c 0 d - 1 t c 0 d p w m o u t p u t t c 0 d i r = 0 . . . 0 x f d 0 x f e 0 x f f t c 0 r t c 0 r + 1 t c 0 r + 2 . . . e n a b l e t c 0 a n d p w m . t c 0 c i s l o a d e d f r o m t c 0 r . p w m o u t p u t s h i g h s t a t u s . t c 0 c = t c 0 d . p w m e x c h a n g e s t o l o w s t a t u s . t c 0 c o v e r f l o w s f r o m 0 x f f t o 0 x 0 0 . t c 0 c i s l o a d e d f r o m t c 0 r . p w m e x c h a n g e s t o h i g h s t a t u s . o n e c o m p l e t e c y c l e o f p w m . n e x t c y c l e . p w m o u t p u t t c 0 d i r = 1 o n e c o m p l e t e c y c l e o f p w m . n e x t c y c l e . p w m o u t p u t t c 0 d i r = 0 p w m 0 o u t = 1 . t h e p i n e x c h a n g e s t o o u t p u t m o d e a n d o u t p u t s p w m s i g n a l a u t o m a t i c a l l y . p w m 0 o u t = 0 . t h e p i n e x c h a n g e s t o l a s t g p i o m o d e ( o u t p u t l o w ) . p w m 0 o u t = 1 . p w m 0 o u t = 0 . p w m o u t p u t t c 0 d i r = 0 p w m 0 o u t = 1 . t h e p i n e x c h a n g e s t o o u t p u t m o d e a n d o u t p u t s p w m s i g n a l a u t o m a t i c a l l y . p w m 0 o u t = 0 . t h e p i n e x c h a n g e s t o l a s t g p i o m o d e ( o u t p u t h i g h ) . p w m 0 o u t = 1 . p w m 0 o u t = 0 . p w m o u t p u t t c 0 d i r = 0 p w m 0 o u t = 1 . t h e p i n e x c h a n g e s t o o u t p u t m o d e a n d o u t p u t s p w m s i g n a l a u t o m a t i c a l l y . p w m 0 o u t = 0 . t h e p i n e x c h a n g e s t o l a s t g p i o m o d e ( i n p u t ) . p w m 0 o u t = 1 . p w m 0 o u t = 0 . h i g h i m p e n d e n c e ( f l o a t i n g ) p w m o u t p u t t c 0 d i r = 1 p w m 0 o u t = 1 . t h e p i n e x c h a n g e s t o o u t p u t m o d e a n d o u t p u t s p w m s i g n a l a u t o m a t i c a l l y . p w m 0 o u t = 0 . t h e p i n e x c h a n g e s t o l a s t g p i o m o d e ( o u t p u t l o w ) . p w m 0 o u t = 1 . p w m 0 o u t = 0 . p w m o u t p u t t c 0 d i r = 1 p w m 0 o u t = 1 . t h e p i n e x c h a n g e s t o o u t p u t m o d e a n d o u t p u t s p w m s i g n a l a u t o m a t i c a l l y . p w m 0 o u t = 0 . t h e p i n e x c h a n g e s t o l a s t g p i o m o d e ( o u t p u t h i g h ) . p w m 0 o u t = 1 . p w m 0 o u t = 0 . p w m o u t p u t t c 0 d i r = 1 p w m 0 o u t = 1 . t h e p i n e x c h a n g e s t o o u t p u t m o d e a n d o u t p u t s p w m s i g n a l a u t o m a t i c a l l y . p w m 0 o u t = 0 . t h e p i n e x c h a n g e s t o l a s t g p i o m o d e ( i n p u t ) . p w m 0 o u t = 1 . p w m 0 o u t = 0 . h i g h i m p e n d e n c e ( f l o a t i n g )
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 84 version 1. 6 8.3.4 tc0 pulse generator function tc0 timer builds in pulse generator function. the pulse generator outputs a pulse, and the pulse width is decided by tc0 timer?s interval time. the pulse generator is controlled by tc0po bit. when tc0po = 0, tc0 is normal timer mode or pwm function mode. when tc0po = 1, tc0 is pulse generator mode. the pulse generator needs a start trigger signal to control tc0 counter and pulse signal output. when tc0po is set as 1, tc0 counter keeps stopping, and tc0c/tc0r registers? va lue is set by program. tc0c value decides the pulse width. when the trigger event occurs, tc0 counter starts to count, and pulse output pin outputs pulse status controlled tc0dir. when tc0 counter overflows, pulse signal finishes and changes to idle status . the tc0c stops counting and reloads new value through tc0r register. in pulse generator mode, the tc0irq is issued as tc0 counter overflow. during pulse generator operating, to change pulse width is through tc0r, not tc0c, or the pulse width would be err or. the pulse output control signal includes two trigger sources, and cm0sf bit controls tc0 pulse generator trigger source. one is pwm0out bit (cm0sf=0), and the other is comparator 0 output edge (cm0sf=1). if the trigger source is pwm0out bit, set pwm0o ut bit to output pulse signal by program, and pwm0out bit is cleared as tc0 counter overflow. to output next pulse is to set pwm0out bit by program again. tc0 rate=fhosc/2=8mhz @fhosc=16mhz tc0c/tc0r 0x00 0x01 0xfe 0xff pulse width (ns) 31875 31750 125 0 tc0 rate=fhosc/4=4khz @fhosc=16mhz tc0c/tc0r 0x00 0x01 0xfe 0xff pulse width (us) 63750 63 500 250 0 tc0 rate=fhosc/256=62.5khz @fhosc=16mhz tc0c/tc0r 0x00 0x01 0xfe 0xff pulse width (us) 4080 40 64 16 0 tc0 rate=fcpu/2=0.5mhz @fcpu=fh osc/16=16mhz/16=1mhz tc0c/tc0r 0x00 0x01 0xfe 0xff pulse width (us) 510 5 08 2 0 tc0 rate=fcpu/256=3.90625khz @fcpu=fhosc/16=16mhz/16=1mhz tc0c/tc0r 0x00 0x01 0xfe 0xff pulse width (us) 65280 65 024 256 0 ? tc0po=1, cm0sf=0: tc0enb must be set as 1. tc0 8 - bit binary up counter is controlled by pwm0out bit. if pwm0out bit is set as 1 by program, tc0 starts to count. if tc0 overflows, tc0 stops counting, pwm0out bit is cleared automatically, tc0irq is issued, and tc0c reloads new value from tc0r. it is necessa ry to set pwm0out = 1 by program making tc0 counts again. if the trigger is comparator 0 output edge (rising edge and falling edge controlled by comparator control register?s cm0g bit), pulse starts to output as trigger edge condition occurrence. when tc0 overflows, pulse output pin returns to idle status. t c 0 c c o u n t e r i n i t i a l v a l u e , t c 0 r = m t c 0 e n b t c 0 o v e r f l o w s . t c 0 c r e l o a d s f r o m t c 0 r . t c 0 e n b i s s e t b y p r o g r a m . t c 0 e n b i s c l e a r e d b y p r o g r a m . t c 0 s t o p s c o u n t i n g . t c 0 c = t c 0 r . m m + 1 p w m 0 o u t t r i g g e r s i g n a l p w m 0 o u t i s s e t b y p r o g r a m . p w m 0 o u t i s c l e a r e d a s t c 0 o v e r f l o w . 0 x f f t c 0 i r q t c 0 i r q i s s e t a s t c 0 o v e r f l o w . t c 0 i r q i s c l e a r e d b y p r o g r a m . p u l s e g e n e r a t o r . t c 0 d i r = 0 p u l s e g e n e r a t o r . t c 0 d i r = 1
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 85 version 1. 6 ? tc0po=1, cm0sf=1: tc0enb must be set as 1. tc0 8 - bit binary up counter is controlled by comparator 0 output edge condition. the trigger edge can be selected through cm 0g bit. if comparator output edge occurs, tc0 starts to count. if tc0 overflows, tc0 stops counting, tc0irq is issued, and tc0c reloads new value from tc0r. t c 0 c c o u n t e r i n i t i a l v a l u e , t c 0 r = m t c 0 e n b t c 0 o v e r f l o w s . t c 0 c r e l o a d s f r o m t c 0 r . t c 0 e n b i s s e t b y p r o g r a m . t c 0 e n b i s c l e a r e d b y p r o g r a m . t c 0 s t o p s c o u n t i n g . t c 0 c = t c 0 r . m m + 1 c o m p a r a t o r o u t p u t s i g n a l . c m 0 g = 0 , f a l l i n g e d g e . 0 x f f t c 0 i r q t c 0 i r q i s s e t a s t c 0 o v e r f l o w . t c 0 i r q i s c l e a r e d b y p r o g r a m . c o m p a r a t o r o u t p u t s i g n a l . c m 0 g = 1 , r i s i n g e d g e . p u l s e g e n e r a t o r . t c 0 d i r = 0 p u l s e g e n e r a t o r . t c 0 d i r = 1
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 86 version 1. 6 8.3.5 tc0m mode register tc0m is tc0 timer mode control register to con figure tc0 operating mode including tc0 pre - scal a r, clock source, pwm function these configurations must be setup completely before enabling tc0 timer. 0b4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0m tc0enb tc0rate2 tc0rate1 tc0rate0 tc0cks tc 0dir tc0po pwm0out read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 0 pwm0out: pwm0 output and pulse generator output control bit. tc0po = 0: 0 = disable pwm0 output function, and p0.1 is gpio mode. 1 = enable pwm0 output f unction, and pwm0 signal outputs through p0.1 pin. tc0po = 1: 0 = stop pulse output, or the end of pulse output cleared automatically. 1 = enable pulse output. bit 1 tc0po: tc0 pulse output function control bit. 0 = disable. 1 = enable tc0 pulse out put function through p0.1 pin. \ bit 2 tc0dir: pwm0 and pulse generator output phase select bit. 0 = normal phase. high pulse and low idle status. 1 = inverse phase. low pulse and high idle status. bit 3 tc0cks: tc0 clock source select bit. 0 = tc0 clock source is internal system clock (fcpu). 1 = tc0 clock source is high clock source (fhosc). bit [6:4] tc0rate [2:0]: tc0 timer clock source select bits. t c0cks = 0 : 000 = fcpu/256, 001 = fcpu/128, 010 = fcpu/64, 011 = fcpu/32, 100 = fcpu/16, 101 = fcpu/8, 110 = fcpu/4, 111 = fcpu/2. t c0cks = 1: 000 = fhosc/256, 001 = fhosc /128, 010 = fhosc /64, 011 = fhosc /32, 100 = fhosc /16, 101 = fhosc /8, 110 = fhosc /4, 111 = fhosc /2. bit 7 tc0enb: tc0 timer control bit. 0 = disable. 1 = enable. 8.3.6 tc0c c ounting register tc0c is tc0 8 - bit counter. when tc0c overflow occurs, the tc0irq flag is set as 1 and cleared by program. the tc0c decides tc0 interval time through below equation to calculate a correct value. it is necessary to write the correct value to tc0c register and tc0r register first time, and then enable tc0 timer to make sure the fist cycle correct. after one tc0 overflow occurs, the tc0c register is loaded a correct value from tc0r register automatically, not program. 0b5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0c tc0c7 tc0c6 tc0c5 tc0c4 tc0c3 tc0c2 tc0c1 tc0c0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 the equation of t c 0c initial value is as following. t c 0c initial value = 256 - (t c 0 interrupt interval time * tc0 clock rate )
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 87 version 1. 6 8.3.7 tc0 r auto - reload register tc0 timer builds in auto - reload function, and tc0r register stores reload data. when tc0c overflow occurs, tc0c register is loaded data from tc0r register automatically. under tc0 timer countin g status, to modify tc0 interval time is to modify tc0r register, not tc0c register . n ew tc0c data of tc0 interval time will be updated after tc0 timer overflow occurrence, tc0r loads new value to tc0c register. but at the first time to setup tc0m, tc0c an d tc0r must be set the same value before enabling tc0 timer. tc0 is double buffer design. if new tc0r value is set by program, the new value is stored in 1 st buffer. until tc0 overflow occurs, the new value moves to real tc0r buffer. this way can avoid any transitional condition to affect the correctness of tc0 interval time and pwm output signal. 0b6h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0 r tc0 r 7 tc0 r 6 tc0 r 5 tc0 r 4 tc0 r 3 tc0 r 2 tc0 r 1 tc0 r 0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 the equation of t c 0 r initial value is as following. t c 0 r initial value = 256 - (t c 0 interrupt interval time * tc0 clock rate ) ? example: to calculation tc0c and tc0r value to obtain 10ms tc0 interval time. tc0 clock source is fcpu = 16mhz/16 = 1 mhz. select tc0rate=000 (fcpu/128). tc0 interval time = 10ms. tc0 clock rate = 16 mhz/ 16 /128 tc0c/ t c 0 r initial value = 256 - (t c 0 interval time * input clock) = 256 - (10ms * 16mhz / 16 / 128 ) = 256 - ( 10 - 2 * 16 * 10 6 / 16 / 128 ) = b2h 8.3.8 tc0 d pwm duty regi ster tc0d register ? s purpose is to decide pwm duty. in pwm mode, tc0r controls pwm ? s cycle, and tc0d controls the duty of pwm. the operation is base on timer counter value. w h en tc0c = tc0d, the pwm high duty finished and exchange to low level. it is easy to configure tc0d to choose the right pwm ? s duty for application. 0 b7 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t c 0 d t c 0 d 7 t c 0 d 6 t c 0 d 5 t c 0 d 4 t c 0 d 3 t c 0 d 2 t c 0 d 1 t c 0 d 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 the eq uation of t c 0 d initial value is as following. t c 0 d initial value = tc0r + ( pwm high pulse width period / tc0 clock rate ) ? example: to calculate tc0d value to obtain 1/3 duty pwm signal. the tc0 clock source is fcpu = 16mhz/16= 1mhz. select tc0rate=00 0 (fcpu/128). tc0r = b2h. tc0 interval time = 10ms. so the pwm cycle is 100hz. in 1/3 duty condition, the high pulse width is about 3.33ms. tc0d initial value = b2h + ( pwm high pulse width period / t c 0 clock rate ) = b2h + ( 3.33 ms * 16mhz / 16 / 128) = b2h + 1ah = cch
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 88 version 1. 6 8.3.9 tc0 timer operation explame ? tc0 timer configuration : ; reset tc0 timer. clr tc0m ; clear tc0m register. ; set tc0 rate. mov a, #0 nn n 0 0 0 0b b0mov tc0m, a ; set tc0 clock source. b0bclr ftc0cks ; tc0 clock sour ce is fcpu. ; or b0bset ftc0cks ; tc0 clock sour ce is fhosc. ; set tc0c and tc0r register for tc0 interval time. mov a, # value ; tc0c must be equal to tc0r. b0mov tc0c, a b0mov tc0r, a ; clear tc0irq b0bclr ftc0irq ; enab le tc0 timer and interrupt function. b0bset ftc0ien ; enable tc0 interrupt function. b0bset ftc0enb ; enable tc0 timer. ? tc0 pwm configuration : ; reset tc0 timer. clr tc0m ; clear tc0m register. ; set tc0 rate. mov a, #0 nn n 00 0 0b b0mov tc0m, a ; set tc0 clock source. b0bclr ftc0cks ; tc0 clock sour ce is fcpu. ; or b0bset ftc0cks ; tc0 clock sour ce is fhosc. ; set tc0c and tc0r register for pwm cycle . mov a, # value 1 ; tc0c must be equal to tc0r. b0mov tc0c, a b0mov tc0r, a ; set tc0d register for pwm duty. mov a, # value 2 ; tc0d must be greater than tc0r. b0mov tc0 d , a ; set pwm output phase . b0bclr ftc0dir ; high pulse and low idle status. ; or b0bset ftc0dir ; low pulse and high idle status. ; enable pwm and tc0 timer . b0bset fpwm0out ; enable pwm. b0bset ftc0enb ; enable tc0 timer.
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 89 version 1. 6 ? tc0 pulse generator configuration : ; reset tc0 timer. clr tc0m ; clear tc0m register. ; set tc0 rate. mov a, #0 nn n 00 0 0b b0mov tc0m, a ; set tc0 clock source. b0bclr ftc0cks ; tc0 clock sour ce is fcpu. ; or b0bset ftc0cks ; tc0 clock sour ce is fhosc. ; set tc0c and tc0r register for pulse width . mov a, # value 1 ; tc0c must be equal to tc0r. b0mov tc0c, a b0mov tc0r, a ; set pulse output phase . b0bclr ftc0dir ; high pulse and low idle status. ; or b0bset ftc0dir ; low pulse and high idle status. ; set pulse output trigger source. b0bclr fcm0sf ; pulse output tri gger source is pwm0out bit. ; or b0bset fcm0sf ; pulse output trigger source is comparator 0 output edge. ; enable pulse output and tc0 timer . b0bset ftc0po ; enable pulse output function. b0bset ftc0enb ; enable tc0 timer.
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 90 version 1. 6 9 9 9 analog com paraotr 0 9.1 overview the micro - controller builds in one comparator with tc0 pulse generator trigger function. the comparator has normal comparator mode and tc0 pulse output trigger source. the comparator is rail - to - rail structure. that means the input/outpu t voltage is real from vdd~vss. when the positive input voltage is greater than the negative input voltage, the comparator output is high. when the positive input voltage is smaller than the negative input voltage, the comparator output is low. the main pu rposes of comparator 0 are as following. ? normal comparator function : general comparator mode compares the two tensions of positive input terminal and negative input terminal . ? interrupt function: comparator 0 supports interrupt function. when comparator 0 output edge direction equals to edge selection, the cm 0irq actives and the system points program counter to interrupt vector to do interrupt sequence. ? tc0 p ulse generator trigger source : comparator 0 can be tc0 pulse generator trigger source controlled by cm0sf bit. when tc0po = 1 and cm0sf = 1, comparator 0 output status trigger s tc0 pulse generator to outputs pulse signal . ? green mode function: comparator 0 still actives in green mode , but no wake - up function . cm0irq can be latched as trigger event oc currence until system wakes up and returns to normal mode. after system wakes up, the comparator 0 interrupt service routine is executed by program . c m 0 e n g p i o / c m 0 p p i n g p i o c m 0 e n g p i o / c m 0 n p i n g p i o / c m 0 o p i n g p i o c m 0 e n g p i o c m 0 o e n c m 0 g c m 0 o u t f l a g c m 0 i r q c o m p a r a t o r o u t p u t d e l a y : 0 , 1 / f h o s c , 2 / f h o s c , 3 / f h o s c , 4 / f h o s c , 5 / f h o s c , 6 / f h o s c , 7 / f h o s c , 8 / f h o s c , 9 / f h o s c , 1 0 / f h o s c , 1 1 / f h o s c , 1 2 / f h o s c , 1 3 / f h o s c , 1 4 / f h o s c , 1 5 / f h o s c c m 0 d [ 3 : 0 ] c m 0 s f t c 0 p u l s e g e n e r a t o r + _ v d d v s s
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 91 version 1. 6 9.2 normal comparator mo de comparator pins are shared with gpio controlled by cm0en bit. when cm0en=1, cm0n pin is enabled connected to comparator negative terminal, and cm0p pin is enabled connected to comparator positive terminal. cm0oen controls comparator output connected to gpio or not. when cm0oen=1, comparator output terminal is connected to cm0o pin and isolate gpio function. when cm0oen=0, comparator output status can be read through cm0out flag and cm0o pin is gpio mode. ? note: the comparator enable condition is fixed cm0en=1, or the comparato r pins are gpio mode and comparator is disabled. the cm0out and cm0irq bits indicate the comparator result. the cm0out shows the comparator result immediately, but the cm0irq only indicates the event of the comparator result. the event condition is con trolled by register and includes rising edge (cm0out changes from low to high) and falling edge (cm0out changes from high to low) controlled by cm0g bit. when cm0g = 0, the comparator 0 interrupt trigger direction is falling edge. when cm0g = 1, the compar ator 0 interrupt trigger direction is rising edge. ? note: cm0out is comparator raw output without latch. it varies depend on the comparator process result. but the cm0irq is latch comparator output result. it must be cleared by program. comparator su pports interrupt function. the interrupt trigger condition can be selected through cm0g bit including rising edge and falling edge. if cm0g = 0, comparator output trigger edge is falling edge. if cm0g = 1, comparator output trigger edge is rising edge. the edge detection is from comparator output signal through delay processor. when comparator output edge event occurs and equal cm0g condition, cm0irq flag is issued. if cm0ien = 1, program counter points to interrupt vector to execute interrupt service routi ne. c m 0 n c m 0 o c m 0 p + - c o m p a r a t o r c o m p a r a t o r i n t e r n a l l o g i c c m 0 n c m 0 o = g p i o c m 0 p + - c o m p a r a t o r c o m p a r a t o r i n t e r n a l l o g i c c m 0 e n = 1 , c m 0 o e n = 1 c m 0 e n = 1 , c m 0 o e n = 0 c m 0 o u t c m 0 i r q , c m 0 g = 0 f a l l i n g e d g e c m 0 i r q , c m 0 g = 1 r i s i n g e d g e c m 0 i r q s e t s a s f a l l i n g e d g e . c m 0 i r q s e t s a s f a l l i n g e d g e . c m 0 i r q s e t s a s r i s i n g e d g e . c m 0 i r q s e t s a s r i s i n g e d g e . * . c m 0 i r q i s c l e a r e d b y p r o g r a m .
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 92 version 1. 6 comparator 0 compares positive terminal?s voltage and negative terminal?s voltage, and then output result to output pin. when v+ > v - , comparator outputs high status. when v+ < v - , comparator outputs low status. compara tor output terminal builds in delay control block to achieve output hysteresis to filter output transition condition. the delay option has 16 - step including no delay, 1/fhosc, 2/fhosc, 3/fhosc, 4/fhosc, 5/fhosc, 6/fhosc, 7/fhosc, 8/fhosc, 9/fhosc, 10/fhosc , 11/fhosc, 12/fhosc, 13/fhosc, 14/fhosc, 15/fhosc controlled by cm0d[3:0] bits. cm0d[ 3 :0] 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b no 1/fhosc 2/fhosc 3/fhosc 4/fhosc 5/fhosc 6/fhosc 7/fhosc delay time (us) fhosc=16mhz 0 0.0625 0.125 0.1875 0. 25 0.3125 0.375 0.4375 delay time (us) fhosc=4mhz 0 0.25 0.5 0.75 1 1.25 1.5 1.75 cm0d[ 3 :0] 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b 8/fhosc 9/fhosc 10/fhosc 11/fhosc 12/fhosc 13/fhosc 14/fhosc 15/fhosc delay time (us) fhosc=16mhz 0.5 0.5625 0.625 0.6875 0.75 0.8125 0.875 0.9375 delay time (us) fhosc=4mhz 2 2.25 2.5 2.75 3 3.25 3.5 3.75 c m 0 p c m 0 n c m 0 o u t w i t h o u t d e l a y . c m 0 o u t w i t h d e l a y . t h e d e l a y t i m e i s c o n t r o l l e d b y c m 0 d [ 3 : 0 ] b i t s .
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 93 version 1. 6 9.3 comparator 0 special fucniton besides normal comparator function, comparator 0 builds in a special mode to trigger tc0 pulse generator through comparator output edge and controlled by cm0sf bit. when cm0sf=1, comparator 0 special mode is enabled. if comparator 0 output trigger condition occurs, tc0 pulse generator is triggered to output a pulse signal, and comparator interrupt function actives. more detail operation is referred to tc0 pulse generator contents. tc0 pulse generator output signal without delay. tc0 pulse generator output signal with delay. c m 0 p c m 0 n c m 0 o u t w i t h o u t d e l a y . t c 0 p u l s e g e n e r a t o r i d l e h i g h . f a l l i n g e d g e t r i g g e r . t c 0 p u l s e g e n e r a t o r i d l e h i g h . r i s i n g e d g e t r i g g e r . t c 0 p u l s e g e n e r a t o r i d l e l o w . f a l l i n g e d g e t r i g g e r . t c 0 p u l s e g e n e r a t o r i d l e l o w . r i s i n g e d g e t r i g g e r . c m 0 p c m 0 n c m 0 o u t w i t h d e l a y . t c 0 p u l s e g e n e r a t o r i d l e h i g h . f a l l i n g e d g e t r i g g e r . t c 0 p u l s e g e n e r a t o r i d l e h i g h . r i s i n g e d g e t r i g g e r . t c 0 p u l s e g e n e r a t o r i d l e l o w . f a l l i n g e d g e t r i g g e r . t c 0 p u l s e g e n e r a t o r i d l e l o w . r i s i n g e d g e t r i g g e r . c o m p a r a t o r o u t p u t d e l a y .
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 94 version 1. 6 9.4 comparator mode register 09ch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cm0 m cm0en cm0oen cm0out cm0 sf cm0g - - - read/write r/w r/w r r/w r/w - - - after reset 0 0 0 0 0 - - - bit 3 cm0g: comparator output trigger direction control bit. 0 = falling edge trigger. comparator output status is from high to low as cm0p < cm0n. 1 = rising edge trigger. comparator output status is from low to high as cm0p > cm0n. bit 4 cm0sf: comparator 0 special mode control bit. 0 = disable. comparator 0 is normal comparato r function. 1 = enable. comparator 0 output edge triggers tc0 pulse generator. bit 5 cm0out: comparator 0 output flag bit. 0 = cm0p voltage is less than cm0n voltage. 1 = cm0p voltage is larger than cm0n voltage. bit 6 cm0oen: comparator 0 output p in control bit. 0 = disable. cm0o is gpio mode. 1 = enable. cm0o is comparator output pin and isolate gpio function. bit 7 cm0en: comparator 0 control bit. 0 = disable. comparator pins are gpio mode. 1 = enable. cm0n and cm0p pins are comparator mode. c m0o is controlled by cm0oen bit. 09 a h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmdb0 cm1d3 cm1d2 cm1d1 cm1d0 cm0d3 cm0d2 cm0d1 cm0d0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit [3:0] cm0d[3:0]: comparator 0 de - bo unce time control bit. 0000=no delay, 0001= 1/fhosc, 0010=2/fhosc, 0011=3/fhosc, 0100=4/fhosc, 0101=5/fhosc, 0110=6/fhosc, 0111=7/fhosc, 1000=8/fhosc, 1001=9/fhosc, 1010=10/fhosc, 1011=11/fhosc, 1100=12/fhosc, 1101=13/fhosc, 1110=14/fhosc, 1111=15/fhosc . 9.5 c omparator application notice the comparator is to compares the positive voltage and negative voltage to output result. the positive and negative sources are analog signal. in hardware application circuit, the comparator input pins must be connected a 0.1uf comparator to reduce power noise and make the input signal more stable. the application circuit is as following . m c u c m n n 0 . 1 u f c m n p 0 . 1 u f c m n o c o m p a r a t o r o u t p u t c o m p a r a t o r n e g a t i v e i n p u t c o m p a r a t o r p o s i t i v e i n p u t
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 95 version 1. 6 9.6 comparator 0 operati on explame ? comparator 0 configuration : ; reset comparator 0. clr cm0m ; clear cm0m register. ; set comparator 0 function mode . b0bclr fcm0sf ; n o rmal comparator mode. ; or b0bset fcm0sf ; special function mode. ; set comparator 0 output pin . b0bclr fcm0oen ; disable comparator 0 output pin. ; or b0bset fcm 0oen ; enable comparator 0 output pin. ; set comparator 0 interrupt trigger edge . b0bclr fcm0g ; falling edge. ; or b0bset fcm0g ; rising edge. ; set comparator 0 output de - bounce. b0mov a, cmdb0 ; set cm0d[3:0] for comparator outp ut de - bounce. and a, # 1111 0000 b or a, #0000 n n nn b b0mov cmdb0, a ; clear cm0irq b0bclr f cm0 irq ; enable comparator 0 and interrupt function. b0bset fcm0ien ; enable comparator 0 interrupt function. b0bset fcm0en ; enable compara tor 0.
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 96 version 1. 6 1 1 1 0 0 0 analog comparaotr 1 10.1 overview the micro - controller builds in one comparator with stopping tc0 pulse generator function. the comparator has normal comparator mode and stopping tc0 pulse output trigger source. the comparator is rail - to - rail struc ture. that means the input/output voltage is real from vdd~vss. when the positive input voltage is greater than the negative input voltage, the comparator output is high. when the positive input voltage is smaller than the negative input voltage, the compa rator output is low. the comparator builds in internal reference voltage connected to comparator positive terminal, and comparator positive input pin can be gpio mode as enabling internal reference voltage source . t he main purposes of comparator 1 are as f ollowing. ? normal comparator function : general comparator mode compares the two tensions of positive input terminal and negative input terminal . ? interrupt function: comparator 1 supports interrupt function. when comparator 1 output edge direction equals to edge selection, the cm1 irq actives and the system points program counter to interrupt vector to do interrupt sequence. ? tc0 p ulse generator trigger stopping source : comparator 1 can be tc0 pulse generator stopping trigger source controlled by cm1sf bit. when tc0po = 1 and cm 1 sf = 1, comparator 1 output status trigger s tc0 pulse generator to stop outputting pulse signal . ? green mode function: comparator 1 still actives in green mode , but no wake - up function . cm1irq can be latched as trigger event occurre nce until system wakes up and returns to normal mode. after system wakes up, the comparator 1 interrupt service routine is executed by program . c m 1 e n g p i o / c m 1 p p i n g p i o c m 1 e n g p i o / c m 1 n p i n g p i o / c m 1 o p i n g p i o c m 1 e n g p i o c m 1 o e n c m 1 g c m 1 o u t f l a g c m 1 i r q c o m p a r a t o r o u t p u t d e l a y : 0 , 2 / f c p u , 4 / f c p u , 6 / f c p u , 8 / f c p u , 1 0 / f c p u , 1 2 / f c p u , 1 4 / f c p u , 1 6 / f c p u , 1 8 / f c p u , 2 0 / f c p u , 2 2 / f c p u , 2 4 / f c p u , 2 6 / f c p u , 2 8 / f c p u , 3 0 / f c p u c m 1 d [ 3 : 0 ] c m 1 s f s t o p t c 0 p u l s e g e n e r a t o r + _ v d d v s s c m 1 r s [ 2 : 0 ] 0 . 2 * v d d 0 . 3 * v d d 0 . 4 * v d d 0 . 5 * v d d 0 . 6 * v d d 0 . 7 * v d d 0 . 8 * v d d i n t e r f a c e r e f e r e n c e v o l t a g e s o u r c e
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 97 version 1. 6 10.2 normal comparator mo de c omparator pins are shared with gpio controlled by cm1en bit. when cm1en=1, cm1n pin is enabled connected to comparator negative terminal. comparator positive terminal is controlled by cm1rs[2:0] bits. when cm1rs[2:0]=000b, comparator positive terminal is from cm1p pin, and gpio function is isolated. when cm1rs [2:0]=001b~111b, comparator positive terminal is connected to internal reference voltage source including 7 - level which are 0.2*vdd, 0.3*vdd, 0.4*vdd, 0.5*vdd, 0.6*vdd, 0.7*vdd, 0.8*vdd, and cm1p pin is gpio mode. cm1oen controls comparator output connecte d to gpio or not. when cm1oen=1, comparator output terminal is connected to cm1o pin and isolate gpio function. when cm1oen=0, comparator output status can be read through cm1out flag and cm1o pin is gpio mode. ? note: the com parator enable condition is fixed cm1en=1, or the comparator pins are gpio mode and comparator is disabled. the cm1out and cm1irq bits indicate the comparator result. the cm1out shows the comparator result immediately, but the cm1irq only indicates the event of the comparator result. the event condition is controlled by register and includes rising edge (cm1out changes from low to high) and falling edge (cm1out changes from high to low) controlled by cm1g bit. when cm1g = 0, the comparator 1 interrupt t rigger direction is falling edge. when cm1g = 1, the comparator 1 interrupt trigger direction is rising edge. ? note: cm1out is comparator raw output without latch. it varies depend on the comparator process result. but the cm1irq is latch comparator outp ut result. it must be cleared by program. c m 1 n c m 1 o c m 1 p + - c o m p a r a t o r c o m p a r a t o r i n t e r n a l l o g i c c m 1 n c m 1 o c m 1 p = g p i o + - c o m p a r a t o r c o m p a r a t o r i n t e r n a l l o g i c i n t e r n a l r e f e r e n c e v o l t a g e c m 1 n c m 1 o = g p i o c m 1 p + - c o m p a r a t o r c o m p a r a t o r i n t e r n a l l o g i c c m 1 n c m 1 o = g p i o c m 1 p = g p i o + - c o m p a r a t o r c o m p a r a t o r i n t e r n a l l o g i c i n t e r n a l r e f e r e n c e v o l t a g e c m 1 e n = 1 , c m 1 o e n = 1 , c m 1 r s [ 2 : 0 ] = 0 0 0 b c m 1 e n = 1 , c m 1 o e n = 1 , c m 1 r s [ 2 : 0 ] = 0 0 1 b ~ 1 1 1 b c m 1 e n = 1 , c m 1 o e n = 0 , c m 1 r s [ 2 : 0 ] = 0 0 0 b c m 1 e n = 1 , c m 1 o e n = 0 , c m 1 r s [ 2 : 0 ] = 0 0 1 b ~ 1 1 1 b
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 98 version 1. 6 comparator supports interrupt function. the interrupt trigger condition can be selected through cm1 g bit including rising edge and falling edge. if cm1 g = 0, comparator output trigger edge is falling edge. if cm1 g = 1, comparator output trigger edge is rising edge. the edge detection is from comparator output signal through delay processor. when comparator output edge event occurs and equal cm1 g condition, cm1 irq flag is issued. if cm1 ien = 1, program counter points to interrupt vector to execute interrupt service routine. comparator 1 compares positive terminal?s voltage and negative terminal?s voltage, and then output result to output pin. when v+ > v - , comparator outputs high status. when v+ < v - , comparator outputs low status. comparator output terminal builds in delay control block to achieve output hysteresis to filter output transition condition. the delay option has 16 - step including no delay, 2/fcpu, 4/fcpu, 6/fcpu, 8/fcp u, 10/fcpu, 14/fcpu, 16/fcpu, 18/fcpu, 20/fcpu, 22/fcpu, 24/fcpu, 26/fcpu, 28/fcpu, 30/fcpu controlled by cm1d[3:0] bits. cm1d[2:0] 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b no 2/fcpu 4/fcpu 6/fcpu 8/fcpu 10/fcpu 12/fcpu 14/fcpu delay time (us) fcpu=fhosc/4 =16mhz/4=4mhz 0 0.5 1 1.5 2 2.5 3 3.5 delay time (us) fcpu=fhosc/16 =16mhz/16=1mhz 0 2 4 6 8 10 12 14 cm1d[2:0] 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b 16/fcpu 18/fcpu 20/fcpu 22/fcpu 24/fcpu 26/fcpu 28/fcpu 30/fcpu delay time ( us) fcpu=fhosc/4 =16mhz/4=4mhz 4 4.5 5 5.5 6 6.5 7 7.5 delay time (us) fcpu=fhosc/16 =16mhz/16=1mhz 16 18 20 22 24 26 28 30 c m 1 o u t c m 1 i r q , c m 1 g = 0 f a l l i n g e d g e c m 1 i r q , c m 1 g = 1 r i s i n g e d g e c m 1 i r q s e t s a s f a l l i n g e d g e . c m 1 i r q s e t s a s f a l l i n g e d g e . c m 1 i r q s e t s a s r i s i n g e d g e . c m 1 i r q s e t s a s r i s i n g e d g e . * . c m 1 i r q i s c l e a r e d b y p r o g r a m . c m 1 p c m 1 n c m 1 o u t w i t h o u t d e l a y . c m 1 o u t w i t h d e l a y . t h e d e l a y t i m e i s c o n t r o l l e d b y c m 1 d [ 3 : 0 ] b i t s .
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 99 version 1. 6 10.3 comparator 1 special fucniton besides normal comparator function, comparator 1 builds in a speci al mode to stop tc0 pulse generator output signal . the special mode is to trigger tc0 pulse generator stopping output through comparator output edge and controlled by cm1sf bit. when cm1sf=1, comparator 1 special mode is enabled. if comparator 1 output tri gger condition occurs, tc0 pulse generator function is disabled to turn off extern device . in this condition, tc0po , tc0enb and cm0sf bit s are cleared to disable pulse output function automatically. pulse output pin exchanges to gpio mode and last status. cm1irq is issued to indicate surge event. it is necessary to enable pulse generator by program. stop tc0 pulse output @falling edge trigger, without delay. stop tc0 pulse output @falling edge tri gger, with delay. ? note: if tc0 pulse output is stopped by comparator 1 special mode trigger, the cm1sf and tc0po bits are cleared automatically. it is necessary to set cm1sf, tc0po and tc0enb bits by program to recover tc0 pulse generator function. c m 1 p c m 1 n c m 1 o u t w i t h o u t d e l a y . t c 0 p u l s e g e n e r a t o r . i d l e h i g h . f a l l i n g e d g e t r i g g e r . t c 0 p o b i t c m 1 s f b i t c o r r e c t p u l s e w i d t h . c h a n g e t o i d l e s t a t u s b y f a l l i n g e d g e . d i s a b l e b y f a l l i n g e d g e . d i s a b l e b y f a l l i n g e d g e . e n a b l e b y p r o g r a m . e n a b l e b y p r o g r a m . t c 0 p u l s e g e n e r a t o r . i d l e l o w . f a l l i n g e d g e t r i g g e r . c o r r e c t p u l s e w i d t h . c h a n g e t o i d l e s t a t u s b y f a l l i n g e d g e . c m 1 p c m 1 n c m 1 o u t w i t h d e l a y . t c 0 p u l s e g e n e r a t o r . i d l e h i g h . f a l l i n g e d g e t r i g g e r . t c 0 p o b i t c m 1 s f b i t c o r r e c t p u l s e w i d t h . c h a n g e t o i d l e s t a t u s b y f a l l i n g e d g e . d i s a b l e b y f a l l i n g e d g e . d i s a b l e b y f a l l i n g e d g e . e n a b l e b y p r o g r a m . e n a b l e b y p r o g r a m . t c 0 p u l s e g e n e r a t o r . i d l e l o w . f a l l i n g e d g e t r i g g e r . c o r r e c t p u l s e w i d t h . c h a n g e t o i d l e s t a t u s b y f a l l i n g e d g e .
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 100 version 1. 6 10.4 comparator mode register 09 d h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cm 1 m cm 1 en cm 1 oen cm 1 out cm 1sf cm 1 g cm1rs2 cm1rs1 cm1rs0 read/write r/w r/w r r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit [2:0] cm1rs[2:0]: comparator positive ter minal voltage source select bit. 000 = cm1p pin is comparator positive input pin, and gpio function is isolated. 001 = internal 0.2*vdd. cm1p pin is gpio mode. 010 = internal 0.3*vdd. cm1p pin is gpio mode. 011 = internal 0.4*vdd. cm1p pin is gpio mode. 1 00 = internal 0.5*vdd. cm1p pin is gpio mode. 101 = internal 0.6*vdd. cm1p pin is gpio mode. 110 = internal 0.7*vdd. cm1p pin is gpio mode. 111 = internal 0.8*vdd. cm1p pin is gpio mode. bit 3 cm1 g: comparator output trigger direction control bit. 0 = fa lling edge trigger. comparator output status is from high to low as cm1 p < cm1 n. 1 = rising edge trigger. comparator output status is from low to high as cm1 p > cm1 n. bit 4 cm1 sf: comparator 1 special mode control bit. 0 = disable. comparator 1 is normal comparator function. 1 = enable. comparator 1 output edge triggers tc0 pulse generator stopping . bit 5 cm1 out: comparator 1 output flag bit. 0 = cm1 p voltage is less than cm1 n voltage. 1 = cm1 p voltage is larger than cm1 n voltage. bit 6 cm1 oen: co mparator 1 output pin control bit. 0 = disable. cm1 o is gpio mode. 1 = enable. cm1 o is comparator output pin and isolate gpio function. bit 7 cm1 en: comparator 1 control bit. 0 = disable. comparator pins are gpio mode. 1 = enable. cm1n pin is comparator mode. cm1o is controlled by cm1oen bit. cm1p is controlled by cm1rs[2:0]bits. 09 a h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmdb0 cm1d3 cm1d2 cm1d1 cm1d0 cm 0 d3 cm0 d2 cm0 d1 cm0 d0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit [7:4] cm1d[3:0]: comparator 1 de - bounce time control bit. 0000=no delay, 0001=2 /fcpu, 0010=4/fcpu, 0011=6/fcpu, 0100=8/fcpu, 0101=10/fcpu, 0110=12/fcpu,0111=14/fcpu, 1000=16/fcpu, 1001=18/fcpu, 1010=20/fcpu, 1011=22/fcpu, 1100=24/fcpu, 1101=26/f cpu, 1110=28/fcpu, 1111=30/fcpu
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 101 version 1. 6 10.5 comparator application notice the comparator is to compares the positive voltage and negative voltage to output result. the positive and negative sources are analog signal. in hardware application circuit, the comparator i nput pins must be connected a 0.1uf comparator to reduce power noise and make the input signal more stable. the application circuit is as following . 10.6 comparator 1 operati on explame ? comparator 1 configuration : ; reset compa rator 1 . clr cm1m ; clear cm1m register. ; set comparator 1 positive terminal . mov a, #00000 nnn b ; set cm1rs[2:0] for comparator positive terminal. b0mov cm1m, a ; set comparator 1 function mode . b0bclr fcm1sf ; n o rmal comparator mod e. ; or b0bset fcm1sf ; special function mode. ; set comparator 1 output pin . b0bclr fcm1oen ; disable comparator 1 output pin. ; or b0bset fcm1oen ; enable comparator 1 output pin. ; set comparator 1 interrupt trigger edge . b0bclr fcm1g ; falling edge. ; or b0bset fcm1g ; rising edge. ; set comparator 1 output de - bounce. b0mov a, cmdb0 ; set cm1d[3:0] for comparator output de - bounce. and a, # 0000 1111 b or a, # n n nn 0000 b b0mov cmdb0, a ; clear c m1 irq b0bclr f cm1 irq ; enable comparator 1 and interrupt function. b0bset fcm1ien ; enable comparator 1 interrupt function. b0bset fcm1en ; enable comparator 1. m c u c m n n 0 . 1 u f c m n p 0 . 1 u f c m n o c o m p a r a t o r o u t p u t c o m p a r a t o r n e g a t i v e i n p u t c o m p a r a t o r p o s i t i v e i n p u t
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 102 version 1. 6 1 1 1 1 1 1 analog comparaotr 2 11.1 overview the micro - controller builds in one comparator w ith shrinking tc0 pulse width function. the comparator has normal comparator mode and shrinking tc0 pulse width trigger source. the comparator is rail - to - rail structure. that means the input/output voltage is real from vdd~vss. when the positive input volt age is greater than the negative input voltage, the comparator output is high. when the positive input voltage is smaller than the negative input voltage, the comparator output is low. the comparator builds in internal reference voltage connected to compar ator positive terminal, and comparator positive input pin can be gpio mode as enabling internal reference voltage source . t he main purposes of comparator 2 are as following. ? normal comparator function : general comparator mode compares the two tensions of positive input terminal and negative input terminal . ? interrupt function: comparator 2 supports interrupt function. when comparator 2 output edge direction equals to edge selection, the cm2 irq actives and the system points program counter to interrupt vec tor to do interrupt sequence. ? tc0 p ulse width shrinking source : comparator 2 can be tc0 pulse width shrinking trigger source controlled by cm2sf bit. when tc0po = 1 and cm2 sf = 1, comparator 2 output status trigger s to shrink tc0 pulse width through incre asing tc0r register. ? green mode function: comparator 2 still actives in green mode , but no wake - up function . cm2irq can be latched as trigger event occurrence until system wakes up and returns to normal mode. after system wakes up, the comparator 2 inter rupt service routine is executed by program . c m 2 e n g p i o / c m 2 p p i n g p i o c m 2 e n g p i o / c m 2 n p i n g p i o / c m 2 o p i n g p i o c m 2 e n g p i o c m 2 o e n c m 2 g c m 2 o u t f l a g c m 2 i r q c o m p a r a t o r o u t p u t d e l a y : 0 , 2 / f c p u , 4 / f c p u , 6 / f c p u , 8 / f c p u , 1 0 / f c p u , 1 2 / f c p u , 1 4 / f c p u , 1 6 / f c p u , 1 8 / f c p u , 2 0 / f c p u , 2 2 / f c p u , 2 4 / f c p u , 2 6 / f c p u , 2 8 / f c p u , 3 0 / f c p u c m 2 d [ 3 : 0 ] c m 2 s f i n c r e a s e t c 0 r t o s h r i n k t c 0 p u l s e w i d t h + _ v d d v s s c m 2 r s [ 2 : 0 ] 0 . 2 * v d d 0 . 3 * v d d 0 . 4 * v d d 0 . 5 * v d d 0 . 6 * v d d 0 . 7 * v d d 0 . 8 * v d d i n t e r f a c e r e f e r e n c e v o l t a g e s o u r c e
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 103 version 1. 6 11.2 normal comparator mo de c omparator pins are shared with gpio controlled by cm2 en bit. when cm2 en=1, cm2 n pin is enabled connected to comparator negative terminal. comparator pos itive terminal is controlled by cm2 rs[2:0] bits. when cm2 rs[2:0]=000b, comparator positive terminal is from cm2 p pin, and gpio function is isolated. when cm2 rs[2:0]=001b~111b, comparator positive terminal is connected to internal reference voltage source i ncluding 7 - level which are 0.2*vdd, 0.3*vdd, 0.4*vdd, 0.5*vdd, 0.6*vdd, 0.7*vdd, 0.8*vdd, and cm2 p pin is gpio mode. cm2 oen controls comparator output connected to gpio or not. when cm2 oen=1, comparator output terminal is connected to cm2 o pin and isolate gpio function. when cm2 oen=0, comparator output status can be read through cm2 out flag and cm2 o pin is gpio mode. ? note: the comparator enable condition is fixed cm2en=1, or the comparator pins are gpio mode and comparator is disabled. the cm2out and cm2irq bits indicate the comparator result. the cm2out shows the comparator result immediately, but the cm2irq only indicates the event of the comparator result. the event condition is controlled by register and includes risin g edge (cm2out changes from low to high) and falling edge (cm2out changes from high to low) controlled by cm2g bit. when cm2g = 0, the comparator 2 interrupt trigger direction is falling edge. when cm2g = 1, the comparator 2 interrupt trigger direction is rising edge. ? note: cm2out is comparator raw output without latch. it varies depend on the comparator process result. but the cm2irq is latch comparator output result. it must be cleared by program. c m 2 n c m 2 o c m 2 p + - c o m p a r a t o r c o m p a r a t o r i n t e r n a l l o g i c c m 2 n c m 2 o c m 2 p = g p i o + - c o m p a r a t o r c o m p a r a t o r i n t e r n a l l o g i c i n t e r n a l r e f e r e n c e v o l t a g e c m 2 n c m 2 o = g p i o c m 2 p + - c o m p a r a t o r c o m p a r a t o r i n t e r n a l l o g i c c m 2 n c m 2 o = g p i o c m 2 p = g p i o + - c o m p a r a t o r c o m p a r a t o r i n t e r n a l l o g i c i n t e r n a l r e f e r e n c e v o l t a g e c m 2 e n = 1 , c m 2 o e n = 1 , c m 2 r s [ 2 : 0 ] = 0 0 0 b c m 2 e n = 1 , c m 2 o e n = 1 , c m 2 r s [ 2 : 0 ] = 0 0 1 b ~ 1 1 1 b c m 2 e n = 1 , c m 2 o e n = 0 , c m 2 r s [ 2 : 0 ] = 0 0 0 b c m 2 e n = 1 , c m 2 o e n = 0 , c m 2 r s [ 2 : 0 ] = 0 0 1 b ~ 1 1 1 b
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 104 version 1. 6 comparator supports interrupt function. the inter rupt trigger condition can be selected through cm2 g bit including rising edge and falling edge. if cm2 g = 0, comparator output trigger edge is falling edge. if cm2 g = 1, comparator output trigger edge is rising edge. the edge detection is from comparator o utput signal through delay processor. when comparator output edge event occurs and equal cm2 g condition, cm2 irq flag is issued. if cm2 ien = 1, program counter points to interrupt vector to execute interrupt service routine. comparator 2 compares positive terminal?s voltage and negative terminal?s voltage, and then output result to output pin. when v+ > v - , comparator outputs high status. when v+ < v - , comparator outputs low status. comparator output terminal builds in delay c ontrol block to achieve output hysteresis to filter output transition condition. the delay option has 16 - step including no delay, 2/fcpu, 4/fcpu, 6/fcpu, 8/fcpu, 10/fcpu, 14/fcpu, 16/fcpu, 18/fcpu, 20/fcpu, 22/fcpu, 24/fcpu, 26/fcpu, 28/fcpu, 30/fcpu contr olled by cm2 d[3:0] bits. cm2 d[2:0] 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b no 2/fcpu 4/fcpu 6/fcpu 8/fcpu 10/fcpu 12/fcpu 14/fcpu delay time (us) fcpu=fhosc/4 =16mhz/4=4mhz 0 0.5 1 1.5 2 2.5 3 3.5 delay time (us) fcpu=fhosc/16 =16mhz/16=1mh z 0 2 4 6 8 10 12 14 cm2 d[2:0] 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b 16/fcpu 18/fcpu 20/fcpu 22/fcpu 24/fcpu 26/fcpu 28/fcpu 30/fcpu delay time (us) fcpu=fhosc/4 =16mhz/4=4mhz 4 4.5 5 5.5 6 6.5 7 7.5 delay time (us) fcpu=fhosc/16 =16mhz/16 =1mhz 16 18 20 22 24 26 28 30 c m 2 o u t c m 2 i r q , c m 2 g = 0 f a l l i n g e d g e c m 2 i r q , c m 2 g = 1 r i s i n g e d g e c m 2 i r q s e t s a s f a l l i n g e d g e . c m 2 i r q s e t s a s f a l l i n g e d g e . c m 2 i r q s e t s a s r i s i n g e d g e . c m 2 i r q s e t s a s r i s i n g e d g e . * . c m 2 i r q i s c l e a r e d b y p r o g r a m . c m 2 p c m 2 n c m 2 o u t w i t h o u t d e l a y . c m 2 o u t w i t h d e l a y . t h e d e l a y t i m e i s c o n t r o l l e d b y c m 2 d [ 3 : 0 ] b i t s .
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 105 version 1. 6 11.3 comparator 2 special fucniton besides normal comparator function, comparator 2 builds in a special mode to shrink tc0 pulse width through increasing tc0r register . the special mode is to trigge r increasing tc0r register and tc0 pulse width will be shrunk through comparator output edge and controlled by cm2sf bit. when cm2sf=1, comparator 2 special mode is enabled. if comparator 2 output trigger condition occurs, tc0r register increases 1 to shri nk tc0 pulse width . step 1: when comparator 2 first trigger occurs, tc0r + 1 once to shrink tc0 pulse width. tc0 pulse width reduces a unit time automatically. the hardware checks comparator 2 high tension status at the end of one tc0 pulse signal ? s cycl e . if the comparator output status exchanges , to expand tc0 pulse width through increasing tc0r register by program. step 2: if comparator output status doesn?t exchange , tc0r + 1 at the end of one tc0 pulse signal ? s cycle an d outputs the new pulse until comparator 2 output status exchanges . ? note: if tc0r is increased to 0xff, tc0r will keep 0xff and not increase again, even the comparator output status never occurs exchanging. c m 0 p c m 0 n n o r m a l t c 0 p u l s e g e n e r a t o r c m 2 p c m 2 n t c 0 p u l s e g e n e r a t o r c o m p a r a t o r t r i g g e r ! t c 0 r + 1 . p u l s e w i d t h k e e p s l a s t p e r i o d . t c 0 r + 1 p u l s e w i d t h . a t e n d o f o n e t c 0 p u l s e s i g n a l ? s c y c l e t o c h e c k c o m p a r a t o r 2 s t a t u s e x c h a n g i n g . c m 0 p c m 0 n n o r m a l t c 0 p u l s e g e n e r a t o r c m 2 p c m 2 n t c 0 p u l s e g e n e r a t o r h i g h t e n s i o n ! t c 0 r + 1 . p u l s e w i d t h k e e p s l a s t p e r i o d . t c 0 r + 1 p u l s e w i d t h . h i g h t e n s i o n ! a t t h e e n d o f o n e t c 0 p u l s e s i g n a l ? s c y c l e t o c h e c k c o m p a r a t o r 2 s t a t u s n o t e x c h a n g i n g . t c 0 r + 1 a g a i n . t c 0 r + 2 p u l s e w i d t h . a t t h e e n d o f o n e t c 0 p u l s e s i g n a l ? s c y c l e t o c h e c k c o m p a r a t o r 2 s t a t u s e x c h a n g i n g .
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 106 version 1. 6 11.4 comparato r mode register 09 e h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cm2 m cm2 en cm2 oen cm2 out cm2 sf cm2 g cm2 rs2 cm2 rs1 cm2 rs0 read/write r/w r/w r r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit [2:0] cm2 rs[2:0]: comparator positive terminal volta ge source select bit. 000 = cm2 p pin is comparator positive input pin, and gpio function is isolated. 001 = internal 0.2*vdd. cm2 p pin is gpio mode. 010 = internal 0.3*vdd. cm2 p pin is gpio mode. 011 = internal 0.4*vdd. cm2 p pin is gpio mode. 100 = intern al 0.5*vdd. cm2 p pin is gpio mode. 101 = internal 0.6*vdd. cm2 p pin is gpio mode. 110 = internal 0.7*vdd. cm2 p pin is gpio mode. 111 = internal 0.8*vdd. cm2 p pin is gpio mode. bit 3 cm2 g: comparator output trigger direction control bit. 0 = falling edge trigger. comparator output status is from high to low as cm2 p < cm2 n. 1 = rising edge trigger. comparator output status is from low to high as cm2 p > cm2 n. bit 4 cm2 sf: comparator 2 special mode control bit. 0 = disable. comparator 2 is normal comparator function. 1 = enable. comparator 2 output edge triggers tc0 pulse generator stopping . bit 5 cm2 out: comparator 2 output flag bit. 0 = cm2 p voltage is less than cm2 n voltage. 1 = cm2 p voltage is larger than cm2 n voltage. bit 6 cm2 oen: comparator 2 output pin control bit. 0 = disable. cm2 o is gpio mode. 1 = enable. cm2 o is comparator output pin and isolate gpio function. bit 7 cm2 en: comparator 2 control bit. 0 = disable. comparator pins are gpio mode. 1 = enable. cm2 n pin is comparator mode. cm2 o is controlled by cm2 oen bit. cm2 p is controlled by cm2 rs[2:0]bits. 09 b h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmdb1 - - - - cm2d3 cm2d2 cm2d1 cm2d0 read/write - - - - r/w r/w r/w r/w after reset - - - - 0 0 0 0 bit [7:4] cm2 d[3:0]: compara tor 2 de - bounce time control bit. 0000=no delay, 0001=2 /fcpu, 0010=4/fcpu, 0011=6/fcpu, 0100=8/fcpu, 0101=10/fcpu, 0110=12/fcpu,0111=14/fcpu, 1000=16/fcpu, 1001=18/fcpu, 1010=20/fcpu, 1011=22/fcpu, 1100=24/fcpu, 1101=26/fcpu, 1110=28/fcpu, 1111=30/fcpu
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 107 version 1. 6 11.5 c omparator application notice the comparator is to compares the positive voltage and negative voltage to output result. the positive and negative sources are analog signal. in hardware application circuit, the comparator input pins must be connected a 0.1uf comparator to reduce power noise and make the input signal more stable. the application circuit is as following . 11.6 comparator 2 operati on explame ? comparator 2 configuration : ; reset comparator 2 . clr cm2m ; clear cm2m re gister. ; set comparator 2 positive terminal . mov a, #00000 nnn b ; set cm2rs[2:0] for comparator positive terminal. b0mov cm2m, a ; set comparator 2 function mode . b0bclr fcm2sf ; n o rmal comparator mode. ; or b0bset fcm2sf ; spec ial function mode. ; set comparator 2 output pin . b0bclr fcm2oen ; disable comparator 2 output pin. ; or b0bset fcm2oen ; enable comparator 2 output pin. ; set comparator 2 interrupt trigger edge . b0bclr fcm2g ; falling edge. ; o r b0bset fcm2g ; rising edge. ; set comparator 2 output de - bounce. mov a, #0000 n n nn b ; set cm2d[3:0] for comparator output de - bounce. b0mov cmdb1, a ; clear cm2 irq b0bclr f cm2 irq ; enable comparator 2 and interrupt functio n. b0bset fcm2ien ; enable comparator 2 interrupt function. b0bset fcm2en ; enable comparator 2. m c u c m n n 0 . 1 u f c m n p 0 . 1 u f c m n o c o m p a r a t o r o u t p u t c o m p a r a t o r n e g a t i v e i n p u t c o m p a r a t o r p o s i t i v e i n p u t
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 108 version 1. 6 1 1 1 2 2 2 2k/4k buzzer generator 12.1 overview the mcu builds in buzzer generator to drive external buzzer device. the buzzer generator purpose is to drive 2khz or 4khz buzzer. adjusting buzzer output frequency is through bzm register. the buzzer output pin is shared with gpio. when bzen = 1, the pin outputs buzzer carry signal. w h en bzen = 0, the pin returns to gpio last condition (input mode, output high or output low status). the buzzer frequency is divided from fcpu (instruction cycle) controlled by bzrate bits, and fcpu decides the buzzer frequency. the selection table is as following. bzrate [1:0] buzzer rate division buzzer rate fcpu = 1mhz fcpu = 2mhz fcpu = 4mhz 00 fcpu/256 4khz 8khz 16khz 01 fcpu/512 2khz 4khz 8khz 10 fcpu/1024 1khz 2khz 4khz 11 fcpu/2048 0.5khz 1khz 2khz the buzzer target frequency is 2khz and 4khz. it is important to choice a good fcpu rate to obtain the correct buzzer frequency. the above table shows 2khz/4khz buzzer frequency configurations. 12.2 bzm register 0dch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bzm bzen bzrate1 bzrate0 - - - - - read/write r/w r/w r/w - - - - - after reset 0 0 0 - - - - - bit 7 bzen: buzzer output control bit. 0 = d isable bz output and bz output pin transfers to i/o last status. 1 = e nable bz output and disable gpio function. bit[6:5] bzrate[1:0]: buzzer rate control bits. 00 = fcpu/256 01 = fcpu/512 10 = fcpu/1024 11 = fcpu/2048 ? note: 1. if bzen=0, the buzzer output pin is gpio mode and returns to last status after disabling buzzer output. 2. if bzen=1, the buzzer output pin is buzzer output function and isolates the gpio function. f c p u b z r a t e [ 1 : 0 ] f c p u / 2 5 6 f c p u / 5 1 2 f c p u / 1 0 2 4 f c p u / 2 0 4 8 b z e n g p i o p i n
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 109 version 1. 6 1 1 1 3 3 3 8 channe l analog to digital converter (adc) 13.1 overview the analog to digital converter ( adc ) is sar structure with 8 - input sources and up to 4096 - step resolution to transfer analog signal into 12 - bits digital buffers . the adc builds in 8 - channel input source (ain0~ ain7) to measure 8 different analog signal sources controlled by chs[2:0] and gchs bits. the adc resolution can be selected 8 - bit and 12 - bit resolutions through adlen bit. the adc converting rate can be selected by adcks[1:0] bits to decide adc converting time. the adc reference high voltage includes two source s controlled by avrefh bit . one is internal vdd (avrefh=0), and the other one is external reference voltage input pin from p4.0 pin (avrefh=1). the adc b uild s in p4con register to set pure analog inpu t pin. it is necessary to set p4 as input mode with out pull - up resistor by program. after setup adenb and ads bits, the adc start s to convert analog signal to digital data . when the conversion is complete, the adc circuit will set eoc and adcirq bit s to 1 and the digital data output s in adb and adr register s . if the adcien = 1, the adc interrupt request occurs and executes interrupt service routine when adcirq = 1 after adc converting. if adc interrupt function is enabled (adcien=1), the system will execu te interrupt procedure. the interrupt procedure is system program counter points to interrupt vector (org 8) and executes interrupt service routine after finishing adc converting. clear adcirq by program is necessary in interrupt procedure. a i n 5 / p 4 . 5 a i n 4 / p 4 . 4 a i n 7 / p 4 . 7 a i n 6 / p 4 . 6 a i n 3 / p 4 . 3 a i n 2 / p 4 . 2 a i n 1 / p 4 . 1 a i n 0 / a v r e f h / p 4 . 0 p 4 c o n c h s [ 2 : 0 ] g c h s i n t e r n a l v d d a d c h i g h r e f e r e n c e v o l t a g e a n a l o g i n p u t a d e n b a d s a d c c l o c k c o u n t e r a d c k s [ 1 : 0 ] a d l e n a d b [ 1 1 : 0 ] e o c a d c i r q 8 / 1 2 a v r e f h s a r a d c a d t a d c o f f s e t c a l i b r a t i o n
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 110 version 1. 6 13.2 ad c mode register ad m is adc mode control register to configure adc configurations including adc start, adc channel selection, adc high reference voltage source and adc processing indicator these configurations must be setup completely before starting adc converting. 0b1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adm adenb ads eoc gchs avrefh chs2 chs1 chs0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 7 adenb: adc control bit. in power saving m ode, disable adc to reduce power consumption. 0 = disable adc function. 1 = enable adc function. bit 6 ads: adc start control bit. ads bit is cleared after adc processing automatically. 0 = adc converting stops. 1 = start to execute adc converting. bit 5 eoc: adc status bit. 0 = adc progressing. 1 = end of converting and reset ads bit. bit 4 gchs: adc global channel select bit. 0 = disable ain channel . 1 = enable ain channel . bit 3 avrefh: adc high reference voltage source control bit. 0 = in ternal vdd. p4.0 is gpio or ain0 pin. 1 = enable external reference voltage from p4.0 . bit [2:0] chs[2:0]: adc input channel select bit. 000 = ain0, 001 = ain1, 010 = ain2, 011 = ain3, 100 = ain4, 101 = ain5, 110 = ain6, 111 = ain7 adr register includ es adc mode control and adc low - nibble data buffer. adc configurations including adc clock rate and adc resolution. these configurations must be setup completely before starting adc converting. 0b3h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adr - adcks1 adlen adcks0 adb3 adb2 adb1 adb0 read/write - r/w r/w r/w r r r r after reset - 0 0 0 - - - - bit 6,4 adcks [1:0] : adc?s clock rate select bit. 00 = fcpu/16 , 01 = fcpu/8 , 10 = fcpu/1, 11 = fcpu/2 bit 5 adlen: adc?s resolution select bits. 0 = 8 - bit . 1 = 12 - bit.
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 111 version 1. 6 13.3 adc data buffer registers adc data buffer is 12 - bit length to store adc converter result. the high byte is adb register, and the low - nibble is adr[3:0] bits. the adb register is only 8 - bit register including bit 4~bit11 adc data. to combine adb register and the low - nibble of adr will get full 12 - bit adc data buffer. the adc data buffer is a read - only register and the initial status is unknown after system reset. ? adb[11:4]: in 8 - bit adc mode, the adc data is stored in adb register . ? adb[11:0]: in 12 - bit adc mode, the adc data is stored in adb and adr registers. 0b2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adb adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 read/write r r r r r r r r after reset - - - - - - - - bit[7:0] adb[ 7:0]: 8 - bit adc data buffer and the high - byte data buffer of 12 - bit adc. 0b3h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adr - adcks1 adlen adcks0 adb3 adb2 adb1 adb0 read/write - r/w r/w r/w r r r r after reset - 0 0 0 - - - - bit [3:0] adb [ 3:0]: 12 - bit low - nibble adc data buffer. the ain input voltage v.s. adb output data ain n adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 adb3 adb2 adb1 adb0 0/409 6 *vrefh 0 0 0 0 0 0 0 0 0 0 0 0 1/409 6 *vrefh 0 0 0 0 0 0 0 0 0 0 0 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4094/409 6 *vrefh 1 1 1 1 1 1 1 1 1 1 1 0 4095/409 6 *vrefh 1 1 1 1 1 1 1 1 1 1 1 1 for different applications, users maybe need more than 8 - bit resolution but less than 12 - bit. to process the adb and a dr data can make the job well. first, the adc resolution must be set 12 - bit mode and then to execute adc converter routine. then delete the lsb of adc data and get the new resolution result. the table is as following. adc resolution adb adr adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 adb3 adb2 adb1 adb0 8 - bit o o o o o o o o x x x x 9 - bit o o o o o o o o o x x x 10 - bit o o o o o o o o o o x x 11 - bit o o o o o o o o o o o x 12 - bit o o o o o o o o o o o o o = selected, x = useless ? note: the initial status of adc data buffer including adb register and adr low - nibble after the system reset is unknown .
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 112 version 1. 6 13.4 adc operation descri ption and notic 13.4.1 adc signal format adc sampling voltage range is limited by high/low reference voltage. the adc low reference voltage is vss and not changeable . the adc high reference voltage includes internal vdd and external reference voltage source from p4.0/avrefh pin controlled by avrefh bit. if avrefh=0, adc reference voltage is from internal vdd (mcu power voltage). if av refh=1, adc reference voltage is from external voltage source (p4.0/avrefh). adc reference voltage range limitation is ( adc high reference voltage C low reference voltage) R . adc low reference voltage is vss = 0v. so adc high reference voltage range i s 2v~vdd . the range is adc external high reference voltage range. ? adc internal low reference voltage = 0v. ? adc internal high reference voltage = vdd. (avrefh=0) ? adc external high reference voltage = 2v~vdd. (avrefh=1) adc sampled input signal volta ge must be from adc low reference voltage to adc high reference. if the adc input signal voltage is over the range, the adc converting result is error (full scale or zero). ? adc low reference voltage Q Q 13.4.2 adc convert ing time the adc converting time is from ads=1 (start to adc convert) to eoc=1 (end of adc convert). the converting time duration is depend on adc resolution and adc clock rate. 12 - bit ad c ? s convertin g ti me is 1/(adc clock /4)*16 sec , and the 8 - bit adc converting time is 1/(adc clock /4)*1 2 sec. adc clock source is fcpu and includes fcpu/1, fcpu/2, fcpu/8 and fcpu/16 controlled by adcks[1:0] bits. the adc converting time affects adc perfo rmance. if input high rate analog signal, it is necessary to select a high adc converting rate. if the adc converting time is slower than analog signal variation rate, the adc result would be error. so to select a correct adc clock rate and adc resolution to decide a right adc converting rate is very important. 12 - bit adc conversion time = 1/(adc clock rate /4)*16 sec adlen adcks1 , adcks0 adc clock rate fcpu=4mhz fcpu=16mhz adc converting time adc converting rate adc converting time adc convertin g rate 1 ( 12 - bit) 0 0 fcpu/ 16 1/(4mhz/ 1 6 /4 )*1 6 = 256 us 3.906khz 1/( 16 mhz/ 1 6 /4 )*1 6 = 64 us 15.625khz 0 1 fcpu/8 1/(4mhz/8 /4 )*1 6 = 128 us 7.813khz 1/( 16 mhz/8 /4 )*1 6 = 32 us 31.25khz 1 0 fcpu 1/ ( 4mhz /4) *1 6 = 16 us 62.5khz 1/ ( 16 mhz /4) *1 6 = 4 us 250khz 1 1 fcpu/2 1/(4mhz/2 /4 )*1 6 = 32 us 31.25khz 1/( 16 mhz/2 /4 )*1 6 = 8 us 125khz 8 - bit adc conversion time = 1/(adc clock rate /4)*12 sec adlen adcks1 , adcks0 adc clock rate fcpu=4mhz fcpu=16mhz adc converting time adc converting rate adc converti ng time adc converting rate 0 ( 8 - bit) 0 0 fcpu/ 16 1/(4mhz/ 1 6 /4 )*12 = 192 us 5.208khz 1/( 16 mhz/ 1 6 /4 )*1 2 = 48 us 20.833khz 0 1 fcpu/8 1/(4mhz/8 /4 )*12 = 96 us 10.416khz 1/( 16 mhz/8 /4 )*1 2 = 24 us 41.667khz 1 0 fcpu 1/ ( 4mhz /4) *12 = 12 us 83.333khz 1/ ( 16 mh z /4) *1 2 = 3 us 333.333khz 1 1 fcpu/2 1/(4mhz/2 /4 )*12 = 24 us 41.667khz 1/( 16 mhz/2 /4 )*1 2 = 6 us 166.667khz
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 113 version 1. 6 13.4.3 adc pin configuration adc input channels are shared with port4. adc channel selection is through adchs[2:0] bit. adchs[2:0] value points to th e adc input channel directly. adchs[2 :0]=000 selects ain0. adchs[2 :0]=00 1 selects ain 1 only one pin of port 4 can be configured as adc input in the same time. the pins of port4 configured as adc input channel must be set input mode, disable internal pull - up and enable p4con first by program. after selecting adc input channel through adchs[2:0], set gchs bit as 1 to enable adc channel function. ? the gpio mode of adc input channels must be set as input mode. ? the internal pull - up resistor of adc input chan nels must be disabled. ? p4con bits of adc input channel must be set . the p4.0/ain0 can be adc external high reference voltage input pin when avrefh=1. in the condition, p4.0 gpio mode must be set as input mode and disable internal pull - up resistor. ? th e gpio mode of adc external high reference voltage input pin must be set as input mode. ? the internal pull - up resistor of adc external high reference voltage input pin must be disabled. adc input pins are shared with digital i/o pins. connect an analog s ignal to coms digital input pin, especially, the analog signal level is about 1/2 vdd will cause extra current leakage. in the power down mode, the above leakage current will be a big problem. unfortunate ly, if users connect more than one analog input sign al to port 4 will encounter above current leakage situation. p4con is port4 c onfiguration register. write 1 into p4con [7:0] will configure related port 4 pin as pure analog input pin to avoid current leakage. 0aeh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 b it 1 bit 0 p4con p4con7 p4con6 p4con5 p4con4 p4con3 p4con2 p4con1 p4con0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 bit[4:0] p4con[7:0]: p4.n configuration control bits. 0 = p4.n can be an analog input (adc input) or digital i/o pins. 1 = p4.n is pure analog input, can ? t be a digital i/o pin. ? note: when port 4 .n is general i/o port not adc channel, p4con .n must set to 0 or the port 4 .n digital i/o signal would be isolated .
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 114 version 1. 6 13.5 adc operation examlp e ? adc configuration : ; reset ad c . clr adm ; clear tc0m register. ; set adc clock rate and adc resolution . mov a, #0 n m n 00 0 0b ; nn: adcks[1:0] for adc clock rate. b0mov adr , a ; m: adlen for adc reolution. ; set adc high reference voltage source. b0bclr favrefh ; internal vdd. or b0 bset favrefh ; external reference voltage. ; set adc input channel configuration . mov a, # value 1 ; set p4con for adc input channel. b0mov p4con , a mov a, # value 2 ; set adc input channel as input mode. b0mov p4m , a mov a, # value 3 ; disable adc input channel ? s internal pull - up resistor. b0mov p4ur , a ; enable adc. b0b set f adcenb ; execute adc 100us warm - up time delay loop. call 100usdly ; 100us delay loop. ; select adc input channel. m ov a, # value ; set adchs[2:0] for adc input channel selection. or adm, a ; enable adc input channel. b0bset fgchs ; enable adc interrupt function. b0bclr fadcirq ; clear adc interrupt flag. b0bset fadcien ; enable adc interrupt func tion. ; start to execute adc converting . b0bset fads ? note: 1. when adenb is enabled, the system must be delay 100us to be t he adc warm - up time by program, and then set ads to do adc converting. the 100us delay time is necessary after adenb settin g (not ads setting), or the adc converting result would be error. normally, the adenb is set one time when the system under normal run condition, and do the delay time only one time. 2. in power saving situation like power down mode and green mode, and not us ing adc function, to disable adc by program is necessary to reduce power consumption.
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 115 version 1. 6 ? adc converting operation : ; adc interrupt disable mode . @@: b0bts1 feoc ; check adc processing flag. jmp @b ; eoc=0: adc is processing. b0mov a, adb ; eoc =1: end of adc processing . process adc result. b0mov buf1,a mov a, #00001111b and a, adr b0mov buf2,a ; end of processing adc result. clr feoc ; clear adc processing flag for next adc converting. ; adc interrupt enable mode . org 8 ; interrupt vector. int_sr: ; interrupt service routine. push b0bts1 fadcirq ; check adc interrupt flag. jmp exit_int ; adcirq =0: not adc interrupt request . b0mov a, adb ; adcirq=1: end of adc processing . process adc result. b0mov buf1,a mov a, #00001111b and a, adr b0mov buf2,a ? note: ads i s cleared when the end of adc converting automatically. eoc bit indicates adc processing status immediately and is cleared when ads = 1. users needn t to clear ads b it by program.
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 116 version 1. 6 13.6 adc application circ uit the analog sig nal is inputted to adc input pin ainn/p4.n . the adc input signal must be through a 0.1uf capacitor a . the 0.1uf capacitor is set between adc input pin and vss pin, and must be on the side of the adc input pin as possible. don ? t connect the capacitor ? s ground pin to ground plain directly, and must be through vss pin. the capacitor can reduce the power noise effective coupled with the analog signal. if the adc high reference voltage is from external voltage source, the external high reference is connect ed to avrefh pin (p4.0). the external high reference source must be through a 47uf c capacitor first, and then 0.1uf capacitor b . these capacitors are set between avrefh pin and vss pin, and must be on the side of the avrefh pin as possible. don ? t conn ect the capacitor ? s ground pin to ground plain directly, and must be through vss pin. v c c g n d 0 . 1 u f a n a l o g s i g n a l i n p u t 4 7 u f 0 . 1 u f e x t e r n a l h i g h r e f e r e n c e v o l t a g e m a i n p o w e r t r u n k a i n n / p 4 . n v s s a v r e f h m c u a b c
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 117 version 1. 6 1 1 1 4 4 4 rail to rail op amplifer 14.1 overview the micro - controller builds in one op amp which is rail - to - r a il structure. t h at means the input/outp ut voltage is real from vdd~vss. the rail - to - rail op amp pins are shared with gpio controlled by op en bit. when open=0, op amp pins are gpio mode. when op en=1, gpio pins switch to op amp and isolate gpio path. op pins selection table is as following. op no. open op positive pin op negative pin op output pin op open=0 all pins are gpio mode. op amp is disabled. open=1 opp (vin+) opn (vin - ) opo (vout) ? note: if op - amp disables, these pins exchange to gpio mode and last status. 14.2 op amp register 09fh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 opm - - - - - - - open read/write - - - - - - - r/w after reset - - - - - - - 0 bit 0 open: op amp control bit. 0 = disable. p1.0, p1.1, p1.2 are gpio mode. 1 = enable. p1.0, p1.1, p1.2 are op amp pins . o p e n g p i o / o p p p i n g p i o + _ v d d v s s g p i o / o p n p i n g p i o g p i o / o p o p i n g p i o v o u t v i n + v i n -
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 118 version 1. 6 1 1 1 5 5 5 instruction table f ield mnemonic description c dc z cycle mov a,m a ? m - - ? 1 m mov m,a m ? a - - - 1 o b0mov a,m a ? m (b an k 0) - - ? 1 v b0mov m,a m (bank 0) ? a - - - 1 e mov a,i a ? i - - - 1 b0mov m,i m ? i, m only supports 0x8 0~0x87 registers (e.g. pflag,r,y,z ) - - - 1 xch a,m a ? ? m - - - 1 +n b0xch a,m a ? ? m (bank 0) - - - 1 +n movc r, a ? rom [y,z] - - - 2 adc a,m a ? a + m + c, if occur carry, then c=1, else c=0 ? ? ? 1 a adc m,a m ? a + m + c, if occur carry, then c=1, else c=0 ? ? ? 1 +n r add a,m a ? a + m, if occur carry, then c=1, else c=0 ? ? ? 1 i add m,a m ? a + m, if occur carry, then c=1, else c=0 ? ? ? 1 +n t b0add m,a m (bank 0) ? m (bank 0) + a, if occur carry, then c=1, else c=0 ? ? ? 1 +n h add a,i a ? a + i, if occur carry, then c=1, else c=0 ? ? ? 1 m sbc a,m a ? a - m - /c, if occur borrow, then c=0, else c=1 ? ? ? 1 e sbc m,a m ? a - m - /c, if occur borrow, then c=0, else c=1 ? ? ? 1 +n t sub a,m a ? a - m, if occur borrow, then c= 0, else c=1 ? ? ? 1 i sub m,a m ? a - m, if occur borrow, then c=0, else c=1 ? ? ? 1 +n c sub a,i a ? a - i, if occur borrow, then c=0, else c=1 ? ? ? 1 daa to adjust acc?s data format from hex to dec. ? - - 1 mul a,m r, a ? a * m, the lb of pro duct stored in acc and hb stored in r register. zf affected by acc. - - ? 2 and a,m a ? a and m - - ? 1 l and m,a m ? a and m - - ? 1 +n o and a,i a ? a and i - - ? 1 g or a,m a ? a or m - - ? 1 i or m,a m ? a or m - - ? 1 +n c or a,i a ? a or i - - ? 1 xor a,m a ? a xor m - - ? 1 xor m,a m ? a xor m - - ? 1 +n xor a,i a ? a xor i - - ? 1 swap m a (b3~b0, b7~b4) ? m(b7~b4, b3~b0) - - - 1 p swapm m m(b3~b0, b7~b4) ? m(b7~b4, b3~b0) - - - 1 +n r rrc m a ? rrc m ? - - 1 o rrcm m m ? r rc m ? - - 1 +n c rlc m a ? rlc m ? - - 1 e rlcm m m ? rlc m ? - - 1 +n s clr m m ? 0 - - - 1 s bclr m.b m.b ? 0 - - - 1 +n bset m.b m.b ? 1 - - - 1 +n b0bclr m.b m(bank 0).b ? 0 - - - 1 +n b0bset m.b m(bank 0).b ? 1 - - - 1 +n cmprs a,i zf,c ? a - i, if a = i, then skip next instruction ? - ? 1 + s b cmprs a,m zf,c ? a C m, if a = m, then skip next instruction ? - ? 1 + s r incs m a ? m + 1, if a = 0, then skip next instruction - - - 1+ s a incms m m ? m + 1, if m = 0, then skip next instruction - - - 1 +n +s n decs m a ? m - 1, if a = 0, then skip next instruction - - - 1+ s c decms m m ? m - 1, if m = 0, then skip next instruction - - - 1 +n +s h bts0 m.b if m.b = 0, then skip next instruction - - - 1 + s bts1 m.b if m.b = 1, th en skip next instruction - - - 1 + s b0bts0 m.b if m(bank 0).b = 0, then skip next instruction - - - 1 + s b0bts1 m.b if m(bank 0).b = 1, then skip next instruction - - - 1 + s jmp d pc15/14 ? rompages1/0, pc13~pc0 ? d - - - 2 call d stack ? pc15~pc0, pc15/14 ? rompages1/0, pc13~pc0 ? d - - - 2 m ret pc ? stack - - - 2 i reti pc ? stack, and to enable global interrupt - - - 2 s push to push acc and pflag (except nt0, npd bit) into buffers . - - - 1 c pop to pop acc and pflag (except nt0, npd bit) from buffers . ? ? ? 1 nop no operation - - - 1 note: 1. m is system register or ram. if m is system registers then n = 0, otherwise n = 1. 2. if branch condition is true then s = 1, otherwise s = 0.
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 119 version 1. 6 1 1 1 6 6 6 electrical characte ristic 16.1 absolute maximum rat ing supply voltage (vdd) . - 0.3v ~ 6.0v input in voltage (vin) . vss C 0.2v ~ vdd + 0.2v operating ambient temperature (topr) sn8p2 7 43k , sn8p27 43s, sn8p2742p, sn8p2742s , sn8p274 1 1p, sn8p2741 1 s .. 0 ? c ~ + 70 ? c sn8p27 43kd , sn8p27 43sd, sn8p2742pd, sn8p2742sd. sn8p2741 1 pd, sn8p274 1 1sd . C 4 0 ? c ~ + 8 5 ? c storage ambient temperature (tstor) . C 4 0 ? c ~ + 125 ? c 16.2 e lectrical characteri stic ? dc characteristic (all of voltages refer to vss, vdd = 5.0v, f osc = 4 mhz, fcpu=1mhz, ambient temperature is 25 ? c unless otherwise n ote.) parameter sym. description min. typ. max. unit operat ing voltage vdd normal mode. fcpu = 1mhz 2.2 - 5.5 v normal mode. fcpu = 4mhz 2.4 - 5.5 v ram data retention voltage vdr 1.5 - - v *vdd rise rate vpor vdd rise rate to ensure internal power - on reset 0.05 - - v/ms input low voltage vil1 all input por ts vss - 0.3vdd v vil2 reset pin vss - 0.2vdd v input high voltage vih1 all input ports 0.7vdd - vdd v vih2 reset pin 0.8vdd - vdd v reset pin leakage current ilekg vin = vdd - - 2 ua i/o port input leakage current ilekg pull - up resistor disable, vi n = vdd - - 2 ua i/o port pull - up resistor rup vin = vss , vdd = 3v 100 200 300 k ? vin = vss , vdd = 5v 50 100 150 i/o output source current ioh vop = vdd C 0.5v 8 - - ma sink current iol vop = vss + 0.5v 8 - - *intn trigger pulse width tint0 int0 interrupt request pulse width 2/fcpu - - cycle supply current (disable adc, op - amp, comparator) idd1 run mode (no loading) vdd= 3v, fcpu = 4mhz - 2 - ma vdd= 5v, fcpu = 4mhz - 4 - ma vdd= 3v, fcpu = 1mhz - 1.5 - ma vdd= 5v, fcpu = 1mhz - 3 - ma vdd= 3v, fcpu = 32khz - 20 - ua vdd= 5v, fcpu = 32khz - 45 - ua idd2 slow mode vdd= 3v, ilrc=16khz - 3.5 - ua vdd= 5v, ilrc=32khz - 10 - ua idd3 sleep mode vdd= 5v/3v - 1 2 ua idd4 green mode (no loading, watchdog disable) vdd= 3v, i hrc=16mhz - 0.35 - ma vdd= 5v, ihrc=16mhz - 0.55 - ma vdd= 3v, ext. 32khz x?tal - 6 - ua vdd= 5v, ext. 32khz x?tal - 18 - ua vdd= 3v, ilrc=16khz - 3 - ua vdd= 5v, ilrc=32khz - 5.5 - ua internal high oscillator freq. fihrc internal hi gh rc (ihrc) 25 ? vdd=2.2v~ 5.5v fcpu=fhosc/4~fhosc/16 15.68 16 16.32 mhz - 40 ? ? vdd=2.4v~ 5.5v fcpu=fhosc/4~fhosc/16 15.2 16 16.8 mhz lvd voltage vdet0 low voltage reset level. 25 ? 1.9 2.0 2.1 v low voltage reset level. - 40 ? ? 1.8 2.0 2. 3 v vdet1 low voltage reset/indicator level. 25 ? 2.3 2.4 2.5 v low voltage reset/indicator level. - 40 ? ? 2.2 2.4 2.7 v vdet2 low voltage reset/indicator level. 25 ? 3.5 3.6 3.7 v low voltage reset/indicator level. - 40 ? ? 3.3 3.6 3.9 v * these parameters are for design reference, not tested.
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 120 version 1. 6 ? adc characteristic (all of voltages refer to vss, vdd = 5.0v, f osc = 4 mhz, fcpu=1mhz, ambient temperature is 25 ? c unless otherwise n ote.) parameter sym. description min. typ. max. unit ain0 ~ ai n7 input voltage vani vdd = 5.0v 0 - avrefh v adc reference voltage vref 2 - - v *adc enable time tast ready to start convert after set adenb = 1 100 - - us *adc current consumption i adc vdd=5.0v - 0.6 - ma vdd=3.0v - 0.4 - ma adc clock frequency f adclk vdd=5.0v - - 8m hz vdd=3.0v - - 5m hz adc conversion cycle time f adcyl vdd=2.4v~5.5v 64 - - 1/f adcl k adc sampling rate (set fads=1 frequency) f adsmp vdd=5.0v - - 125 k/sec vdd=3.0v - - 80 k/sec differential nonlinearity dnl vdd=5.0v , avre fh=3.2v, f adsmp =7.8k 1 - - lsb integral nonlinearity inl vdd=5.0v , avrefh=3.2v, f adsmp =7.8k 2 - - lsb no missing code nmc vdd=5.0v , avrefh=3.2v, f adsmp =7.8k 10 11 12 bits adc offset voltage v adc offset non - trimmed - 10 0 +10 mv trimmed - 2 0 +2 m v * these parameters are for design reference, not tested. ? op amp characteristic (all of voltages refer to vss, vdd = 5.0v, slow mode , high clock disable , ambient temperature is 25 ? c unless otherwise n ote.) parameter sym. description min. typ. max. un it *supply current i op unit gain buffer. vdd=3v. opp=vss. - 1 3 0 - ua unit gain buffer. vdd=5v. opp=vss. - 150 - ua common mode input voltage range vcmr vdd=5.0v vss - 0.3 - vdd+0.3 v input offset voltage vos vcm=vss - 3 - +3 mv power supply rejection r atio psrr vcm=vss 50 - 70 db common mode rejection ratio cmrr vcm= - 0.3v~2.5v. vdd=5v. 50 - 80 db open - loop gain (large signal) aol vout=0.2v~vdd - 0.2v. vcm=vss. 90 110 - db maximum output voltage swing vol, voh 0.5v output overdrive. vss+15 mv vdd - 15 mv v output short current isc unit gain buffer. vo = vss , vdd= vpp=3 v . - 1 7 - +1 7 ma unit gain buffer. vo = vss , vdd= vpp= 5 v . - 45 - + 45 ma output slew rate tosr vo = vss to vdd or vdd to vss. 3 - 5 us * these parameters are for design reference, not tested. ? comparator characteristic (all of voltages refer to vss, vdd = 5.0v, f osc = 4 mhz, fcpu=1mhz, ambient temperature is 25 ? c unless otherwise n ote.) parameter sym. description min. typ. max. unit power supply range supply current vcmp icm 2.0 5.5 v vdd=3 v. internal reference disables. 70 ua vdd=5v. internal reference disables. 70 ua quiescent current iq iout=0 0.3 0.6 1 ua input offset voltage vos vcm=vss - 0.5 +0.5 mv response time trs positive input voltage = 1/2*vdd. negative input voltage t ransitions from vss to vdd. 100 ns output slew rate tosr comparator output voltage transitions from vss to vdd. vdd=3v 100 ns vdd=5v 100 ns comparator output voltage transitions from vdd to vss. vdd=3v 100 ns vdd=5v 100 ns common mode input voltage range vcmr vdd=5.0v vss+0.5 vdd - 0.5 v * these parameters are for design reference, not tested.
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 121 version 1. 6 16.3 characteristic graph s the graphs in this section are for design guidance, not tested or guaranteed. in some graphs, the data presented are outside specified operating range. this is for information only and devices are guaranteed to operate properly only within the specified range ( - 40 ~+85 curves are for design reference). .
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 122 version 1. 6 1 1 1 7 7 7 development tool sonix provides ice (in circuit emulation), ide ( integrated development environment) and ev - kit for sn8p2740 development. ice and ev - kit are external hardware devices, and ide is a fri endly user interface for firmware development and emulation. these development tools? version is as following. ? ice: sn8ice2k plus ii. (please install 16mhz crystal in ice to implement ihrc emulation.) ? ice emulation speed maximum: 8 mips @ 5v (e.g. 16mhz c rystal, fcpu = fosc/2). ? ev - kit: ev2740 kit rev: v1.0. ? ide: sonix ide m2ide_v129 and later version. ? writer: mpiii writer. ? writer transition board: sn8p2742 / sn8p2743 17.1 sn8p 2740 ev - kit sonix provides sn8p27 40 series mcu which includes pwm, adc, comparator and op analog functions. these functions aren?t built in sn8ice2k plus 2 . to emulate the functions must be through sn8p27 43 real chip. the real chip p rovid es a n ev - kit to achieve pwm and the analog functions emulations. for sn8p27 43/42 ice emulation, the e v - kit includes op/comparator/pwm/adc / lvd2.4v/3.6v and switch circuits. ev2740 kit pcb outline: ? con 1: connect to sn8ice2k plus 2 jp3 (ev - kit communication bus with ice, control signal, and the others). ? con 2: connect to sn8ice2k plus 2 con1 (includes gp io, ev - kit control signal, and the others). ? s1 : lvd24v/lvd36v control switch. to emulate lvd2.4v flag/reset function and lvd3.6v/flag function switch no. on off lvd24 (1) lvd 2.4v active lvd 2.4v inactive lvd36 (2) lvd 3.6v active lvd 3.6v inactive ? s 2 : sn8p2743 ev - chip r eset key. if ev - kit active fail, press s2 to reset ev - kit real chip (u1). ? jp 23 : gpio connector. ? jp 18: using adc function before, sn8ice2k plus 2 avrefh/vdd jumper pin must be removed. if adc external reference voltage function enable, j p1 8 (avrefh) or p40o pin is external reference voltage input. ? jp1 7: observe cmp0 input/output voltage. ? jp1 6: observe cmp 1 input/output voltage. ? jp 8: observe cmp 2 input/output voltage. ? jp 7: observe op - amp input/output voltage (op3p = opp, op3n = opn, op3o = opo) . ? u 1 : sn8p 2743 ev - chip for analog functions emulation.
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 123 version 1. 6 ? u 4 : sn8p 2743 dip form connector for connecting to user?s target board. vss 1 u 24 vdd xin/p0.6 2 23 p4.7/ain7 xout/p0.5/bz 3 22 p4.6/ain6 rst/vpp/p0.4 4 21 p4.5/ain5 p0.0/int0 5 20 p4 .4/ain4 p0.1/pwm0 6 19 p4.3/ain3/cm0o p0.2/cm0p 7 18 p4.2/ain2/cm1o p0.3/cm0n 8 17 p4.1/ain1/cm2o p1.6/cm1p 9 16 p4.0/ain0/avrefh p1.5/cm1n 10 15 p1.0/opn p1.4/cm2p 11 14 p1.1/opp p1.3/cm2n 12 13 p1.2/opo ? u 10 : sn8p 2742 dip form connector fo r connecting to user?s target board. vss 1 u 20 vdd xin/p0.6 2 19 p4. 5 /ain 5 xout/p0.5/bz 3 18 p4.4/ain4 rst/vpp/p0.4 / p0.1/pwm0 4 17 p4.3/ain3/cm0o p0.2/cm0p 5 16 p4.2/ain2/cm1o p0.3/cm0n 6 15 p4.1/ain1/cm2o p1.6/cm1p 7 14 p4.0/ain0/avrefh p1 .5/cm1n 8 13 p1.0/opn p1.4/cm2p 9 12 p1.1/opp p1.3/cm2n 10 11 p1.2/opo ? c 32 ~c 39: connect 0.1uf capacitors to ain0~ain7 input which are adc channel 0~7 bypass capacitors. ? c 40: connect 0.1uf capacitors to avrefh input which are adc reference voltage by pass capacitors. ? c 13: c mp0 output pin ? s 0.1f bypass capacitor . ? c 22: c mp1 output pin ? s 0.1f bypass capacitor . ? c 18: c mp2 output pin ? s 0.1f bypass capacitor . ? c 17: op - amp negative input pin ? s 0.1f bypass capacitor . ? c 21: op - amp positive input pin ? s 0.1f bypass capacitor . ? c 12: op - amp output pin ? s 0.1f bypass capacitor . ? c 14: cmp0 positive input pin ? s 0.1f bypass capacitor . ? c 15: cmp0 negative input pin ? s 0.1f bypass capacitor . ? c 23: cmp1 positive input pin ? s 0.1f bypass capacitor . ? c 24: cmp1 negative input pin ? s 0.1f bypass capacitor . ? c 19: cmp2 positive input pin ? s 0.1f bypass capacitor . ? c 20: cmp2 negative input pin ? s 0.1f bypass capacitor . ? jp24: chip select (sn8p2742: jumper short, sn8p2743: open). ? jp25: p0.1 output mos circuit power source
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 124 version 1. 6 ev2740 kit schematic: 17.2 ice and ev - kit application noti c 1. sn8ice2k plus 2 power switch must be turned off before you connect the ev 27 40 kit to sn8ice2k plus 2 . 2. connect ev - kit?s con1/con2 to ice?s jp3/ con1. 3. sn8ice2k plus 2 ?s avrefh/vdd jumper pin must be removed. 4. turn on sn8ice 2k plus power switch after user had finished step 1~3. 5. user observes ev - kit ? s power led (d1) is light after turn on sn8ice2k plus power switch . if led (d1) is not light, that means, user contact to sonix ? s agent right now. 6. if user program select chip sn8p2 743, jp24 open. or user program select chip sn8p2742, jp24 short (jumper). 7. it is necessary to connect 16mhz crystal in ice for ihrc_16m mode emulation. 8. when adc function enable. the adm?s bit 3 (favrefh) is set as high. p40o or jp1 8 (avrefh) will be exter nal reference voltage input pin. 9. when adc function enable. the adm?s bit 3 (favrefh) is set as low. p40o will be analog signal input pin. jp1 8 (avrefh) do not connect power device. 10. observe adc internal or external reference voltage is jp1 8 (avrefh) . 11. the op - amp of sn8p27 43 application circuit is as the below figure (op - amp connect).
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 125 version 1. 6 12. when sn8p27 43 ?s op - amp function enable as the above figure. p 12o (jp 23 ) is op - amp?s output. p 11 (jp 23 ) is op - amp?s non - inverse. p1 0 o (jp 23 ) is op - amp?s inverse. 13. if user want s to measure op - amp v+ / v - / vo voltage as the above figure, the real op - amp?s inverse voltage is op3n (jp 7 ). the real op - amp?s non - inverse voltage is op3 p (jp 7 ). the real op - amp?s output voltage is op3 o (jp 7 ). 14. why op - amp connec ting is different with measurement, because op - amp series connection with analog switch internal resistor (ron). 15. when cmp0 function enable. the cm0p/cm0n (jp17) will be external analog signal input pin. the p43o (jp23) will be cmp0 ? s output result. 16. when cm p1 function enable. the cm1p/cm1n (jp16) will be external analog signal input pin. the p42o (jp23) will be cmp1 ? s output result. 17. when cmp2 function enable. the cm2p/cm1n (jp8) will be external analog signal input pin. the p41o (jp23) will be cmp2 ? s output result. 18. when user uses cmp0~cmp2 ? s cm0p/cm0n/cm1p/cm1n/cm2p/cm2n analog function, user must be connecting to jp17/jp16/jp8. when user uses cmp0~cmp2 ? s cm0p/cm0n/cm0o/cm1p/cm1n/cm1o/cm2p/ cm2n/cm2o logic function, user must be connecting to jp23 ? s p02/p03/p 43o/p16/p15/p42o/p14/p13/p41o. 19. when user uses tc0 special function (pulse generator function and tc0 clock source is fcpu.) in ice emulation. if user sets ide breakpoint, the pwm plus generator output status will be unknow n (fcpu stop). 20. when user uses tc0 special function (pulse generator function and tc0 clock source is fhosc.) in ice emulation. if user sets ide breakpoint, the pwm plus generator output will be finished (fhosc still work). a nd the pwm pulse generator output will be back to idle status. 21. whe n user uses cmp1 and cmp2 ? s de - bounce time control (cm1d3~cm1d0, cm2d3~cm2d0 and clock source is fcpu) in ice emulation. if user sets ide breakpoint, the cm0o output will be effected (fcpu stop) 22. when user uses cmp0 ? s de - bounce time control (cm0d3~cm0d0 and clock source is fhosc) in ice emulation. if user sets ide breakpoint, the cm0o output will be not effected (fhosc still work). + _ v d d v s s v o u t v i n - v i n + v s s v s s v d d r 2 1 . 0 1 1 k o h m r t 1 5 0 k o h m / 2 5 d e g r e e r 1 1 0 0 k o h m r 1 2 . 0 1 1 k o h m a i n 1 c o n n e c t t o j p 2 3 ' s p 1 0 o p i n c o n n e c t t o j p 2 3 ' s p 1 2 o p i n c o n n e c t t o j p 2 3 ' s p 1 1 o p i n
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 126 version 1. 6 1 1 1 8 8 8 otp programming pin 18.1 writer transition bo ard socket pin assignment jp3 (mapping to 48 - pin text tool) writer jp1/jp2 dip 1 1 48 dip48 vdd 1 2 vss dip 2 2 47 dip47 clk/pgclk 3 4 ce dip 3 3 46 dip46 pgm/otpclk 5 6 oe/shiftdat dip 4 4 45 dip45 d1 7 8 d0 dip 5 5 44 dip44 d3 9 10 d2 dip 6 6 43 dip43 d5 11 12 d4 dip 7 7 42 dip42 d7 13 14 d6 dip 8 8 41 dip41 vdd 15 16 vpp dip 9 9 40 dip40 hls 17 18 rst dip10 10 39 dip39 - 19 20 alsb/pdb dip11 11 38 dip38 dip12 12 37 dip37 jp1 for writer transition board dip13 13 36 dip36 jp2 for dice and >48 pin pac kage dip14 14 35 dip35 dip15 15 34 dip34 dip16 16 33 dip33 dip17 17 32 dip32 dip18 18 31 dip31 dip19 19 30 dip30 dip20 20 29 dip29 dip21 21 28 dip28 dip22 22 27 dip27 dip23 23 26 dip26 dip24 24 2 5 dip25 p i n 1 p i n 4 8 p i n 2 4 p i n 2 5 4 8 4 0 2 8 1 8 1 4 48 40 28 18 14
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 127 version 1. 6 18.2 programming pin mapp ing: programming pin information of sn8p2740 series chip name sn8p2743k(skdip)/s(sop) sn8p2742p(dip)/s(sop) writer connector ic and jp3 48 - pin text tool pin assignment jp1/jp2 pin number jp1/jp2 pin name ic pin n umber ic pin name jp3 pin number ic pin n umber ic pin name jp3 pin number 1 vdd 24 vdd 36 20 vdd 34 2 gnd 1 vss 13 1 vss 15 3 clk 16 p 4 . 0 28 14 p 4 . 0 28 4 ce - - - - - - 5 pgm 20 p 4.4 32 18 p 4.4 32 6 oe 17 p 4.1 29 1 5 p 4.1 29 7 d1 - - - - - - 8 d0 - - - - - - 9 d3 - - - - - - 10 d2 - - - - - - 11 d5 - - - - - - 12 d4 - - - - - - 13 d7 - - - - - - 14 d6 - - - - - - 15 vdd - - - - - - 16 vpp 4 rst 16 4 rst 18 17 hls - - - - - - 18 rst - - - - - - 19 - - - - - - - 20 alsb/pdb 3 xout/ p 0.5 15 3 xout/ p 0.5 17 programming pin information of sn8p2740 series chip name sn8p274 1 1p ( p - dip)/s(sop) writer connector ic and jp3 48 - pin text tool pin assignment jp1/jp2 pin number jp1/jp2 pin name ic pin number ic pin n ame jp3 pin number ic pin number ic pin name jp3 pin number 1 vdd 1 vdd 17 2 gnd 13 vss 29 3 clk 10 p4.0 26 4 ce - 5 pgm 14 p4.4 30 6 oe 11 p4.1 27 7 d1 - 8 d0 - 9 d3 - 10 d2 - 11 d5 - 12 d4 - 13 d7 - 14 d6 - 15 vdd - 16 vpp 3 rst 19 17 hls - 18 rst - 19 - - 20 alsb/pdb 2 xout/p0.5 18
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 128 version 1. 6 1 1 1 9 9 9 marking definition 19.1 introduction there are many different types in sonix 8 - bit mcu production line. this note listed the production definition of all 8 - bit mcu for order or obtain information. this definition is only for blank otp mcu. 19.2 marking indetificati on system 19.3 marking example ? wafer, dice: name rom type device package temperature materi al s8 p2743 w otp 2743 wafer 0 ~70 - sn8 p2743 h otp 2743 dice 0 ~70 - ? green package: name rom type device package temperature material sn8p2 743kg otp 2743 sk - dip 0 ~70 green package sn8p2 743sg otp 2743 sop 0 ~70 green package sn8p2 743kdg otp 2743 sk - dip - 40 ~85 green package sn8p2 743sdg otp 2743 sop - 40 ~85 green package sn8p2 742pg otp 2743 dip 0 ~70 green package sn8p2 742sg otp 2743 sop 0 ~70 green package sn8p2 742pdg otp 2743 dip - 40 ~85 green package sn8p2 742sdg otp 2743 sop - 40 ~85 green package t i t l e s o n i x 8 - b i t m c u p r o d u c t i o n r o m t y p e m a t e r i a l b = p b - f r e e p a c k a g e g = g r e e n p a c k a g e t e m p e r a t u r e r a n g e - = 0 ~ 7 0 s h i p p i n g p a c k a g e w = w a f e r , h = d i c e k = s k d i p , p = p - d i p , s = s o p d e v i c e 2 7 4 3 2 7 4 2 2 7 4 1 1 s n 8 x p a r t n o . x x x d = - 4 0 ~ 8 5 p = o t p
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 129 version 1. 6 sn8p274 1 1 pg otp 2743 dip 0 ~70 green package sn8p274 1 1 sg otp 2743 sop 0 ~70 green package sn8p274 1 1 pdg otp 2743 dip - 40 ~85 green package sn8p274 1 1 sdg otp 2743 sop - 40 ~85 green package ? pb - free package: name rom type device package temperature material sn8p2 743k b otp 2743 sk - dip 0 ~70 pb - free package sn8p2 743s b otp 2743 sop 0 ~70 pb - free package sn8p2 743kd b otp 2743 sk - dip - 40 ~85 pb - free package sn8p2 743sd b otp 2743 sop - 40 ~85 pb - free package sn8p2 742p b otp 2743 dip 0 ~70 pb - free package sn8p2 742s b ot p 2743 sop 0 ~70 pb - free package sn8p2 742pd b otp 2743 dip - 40 ~85 pb - free package sn8p2 742sd b otp 2743 sop - 40 ~85 pb - free package sn8p2 741 1 p b otp 2743 dip 0 ~70 pb - free package sn8p2 741 1 s b otp 2743 sop 0 ~70 pb - free package sn8p2 741 1 pd b otp 2743 dip - 40 ~85 pb - free package sn8p2 741 1 sd b otp 2743 sop - 40 ~85 pb - free package 19.4 datecode system x x x x x x x x x y e a r m o n t h 1 = j a n u a r y 2 = f e b r u a r y . . . . 9 = s e p t e m b e r a = o c t o b e r b = n o v e m b e r c = d e c e m b e r s o n i x i n t e r n a l u s e d a y 1 = 0 1 2 = 0 2 . . . . 9 = 0 9 a = 1 0 b = 1 1 . . . . 0 3 = 2 0 0 3 0 4 = 2 0 0 4 0 5 = 2 0 0 5 0 6 = 2 0 0 6 . . . .
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 130 version 1. 6 2 2 2 0 0 0 package information 20.1 sk - dip 24 pin symbols min nor max min nor max (inch) (mm) a - - 0.210 - - 5.334 a1 0.015 - 0.381 - - a2 0.125 0.130 0.135 3.175 3.302 3.429 d 0.735 0.755 0.775 18.669 19.177 19.685 e 0.30 bsc 7.620 bsc e1 0.253 0.258 0.263 6.426 6.553 6.680 l 0.115 0.130 0.150 2.921 3.302 3.810 b 0.335 0.355 0.375 8.509 9.017 9 .525 ? 0 7 15 0 7 15
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 131 version 1. 6 20.2 sop 24 pin symbols min nor max min nor max (inch) (mm) a - - 0.069 - - 1.753 a1 0.004 - 0.010 0.102 - 0.254 d 0.612 0.618 0.624 15.545 15.697 15.850 e 0.292 0.296 0.299 7.417 7.518 7.595 h 0.40 5 0.412 0.419 10.287 10.465 10.643 l 0.021 0.031 0.041 0.533 0.787 1.041 ? 0 4 8 0 4 8
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 132 version 1. 6 20.3 p - dip 20 pin symbols min nor max min nor max (inch) (mm) a - - 0.210 - - 5.334 a1 0.015 - - 0.381 - - a2 0.125 0.130 0.135 3.175 3.30 2 3.429 d 0. 980 1.030 1.060 2 4 . 89 2 2 6 . 162 2 6 . 924 e 0.300 7.620 e1 0.245 0.250 0.255 6.223 6.350 6.477 l 0.115 0.130 0.150 2.921 3.302 3.810 b 0.335 0.355 0.375 8.509 9.017 9.525 ? 0 7 15 0 7 15
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 133 version 1. 6 20.4 sop 20 pin symbols min nor max min no r max (inch) (mm) a 0.093 0.099 0.104 2.362 2.502 2.642 a1 0.004 0.008 0.012 0.102 0.203 0.305 d 0.496 0. 502 0.508 12.598 12.751 12.903 e 0.291 0.295 0.299 7.391 7.493 7.595 h 0.394 0.407 0.419 10.008 10.325 10.643 l 0.016 0.033 0.050 0.406 0.838 1 .270 ? 0 4 8 0 4 8
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 134 version 1. 6 20.5 p - dip 16 pin symbols min nor max min nor max (inch) (mm) a - - 0.210 - - 5.334 a1 0.015 - - 0.381 - - a2 0.125 0.130 0.135 3.175 3.302 3.429 d 0.735 0.775 0.775 18.669 19.177 19.685 e 0.300bsc 7.620bsc e1 0.245 0.250 0.255 6.223 6.350 6.477 l 0.115 0.130 0.150 2.921 3.302 3.810 b 0.335 0.355 0.375 8.509 9.017 9.525 ? 0 7 15 0 7 15
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 135 version 1. 6 20.6 so p 16 pin symbols min nor max min nor max (inch) (mm) a - - 0.069 - - 1.75 a1 0.004 - 0.010 0.10 - 0.25 a2 0.049 - 1.25 - - b 0.012 - 0.020 0.31 - 0.51 c 0.004 - 0.010 0.10 - 0.25 d 9.90bsc 9.90bsc e 6.00bsc 6.00bsc e1 3.90bsc 3.90bsc e 1.27bsc 1.27bsc h 0.016 - 0.050 0.40 - 1.27 l 0.010 - 0.020 0.25 - 0.50 ? 0 - 8 0 - 8
sn8 p 2740 series adc, op - amp, comparator 8 - b it m icro - c ontroller sonix tec hnology co., ltd page 136 version 1. 6 sonix reserves the right to make change without further notice to any products herein to improve reliability, function or design . sonix does not assume any liability arising out of the application or use of any product or circuit described herein; neither does i t convey any license under its patent rights nor the rights of others. sonix products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or susta in life, or for any other application in which the failure of the sonix product could create a situation where personal injury or death may occur. should buyer purchase or use sonix products for any such unintended or unauthorized application. buyer shall indemnify and hold sonix and its officers , employees, subsidiaries, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manufacture of the part. main office: address: 10f - 1, no.36, taiyuan street, chupei city, hsinchu, taiwan r.o.c . tel: 886 - 3 - 560 0888 fax: 886 - 3 - 560 0889 taipei office: address: 15f - 2, no.171, song ted road, taipei, taiwan r.o.c. tel: 886 - 2 - 2759 1980 fax: 886 - 2 - 2759 8180 hong kong office: unit 1519 , chevalier commercial centre, no.8 wang hoi road , kowloon bay, hong kong. t el : 852 - 2723 - 8086 f ax : 852 - 2723 - 9179 technical support by email : sn8fae@sonix.com.tw

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